4 * SPDX-License-Identifier: GPL-2.0+
15 #include <fdt_support.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
22 #include <asm/arch/fsl_serdes.h>
23 #include <asm/arch/soc.h>
25 #include "../common/qixis.h"
26 #include "ls1088a_qixis.h"
27 #include "../common/vid.h"
28 #include <fsl_immap.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 int board_early_init_f(void)
34 fsl_lsch3_early_init_f();
38 #ifdef CONFIG_FSL_QIXIS
39 unsigned long long get_qixis_addr(void)
41 unsigned long long addr;
43 if (gd->flags & GD_FLG_RELOC)
44 addr = QIXIS_BASE_PHYS;
46 addr = QIXIS_BASE_PHYS_EARLY;
49 * IFC address under 256MB is mapped to 0x30000000, any address above
50 * is mapped to 0x5_10000000 up to 4GB.
52 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
58 #if defined(CONFIG_VID)
59 int init_func_vid(void)
61 if (adjust_vdd(0) < 0)
62 printf("core voltage not adjusted\n");
68 #if !defined(CONFIG_SPL_BUILD)
73 static const char *const freq[] = {"100", "125", "156.25",
77 #ifdef CONFIG_TARGET_LS1088AQDS
78 printf("Board: LS1088A-QDS, ");
80 printf("Board: LS1088A-RDB, ");
83 sw = QIXIS_READ(arch);
84 printf("Board Arch: V%d, ", sw >> 4);
86 #ifdef CONFIG_TARGET_LS1088AQDS
87 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
89 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
92 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
94 sw = QIXIS_READ(brdcfg[0]);
95 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
101 #ifdef CONFIG_TARGET_LS1088AQDS
110 printf("vBank: %d\n", sw);
123 sw = QIXIS_READ(brdcfg[0]);
124 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
125 if (sw == 0 || sw == 4)
134 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
138 #ifdef CONFIG_TARGET_LS1088AQDS
139 printf("FPGA: v%d (%s), build %d",
140 (int)QIXIS_READ(scver), qixis_read_tag(buf),
141 (int)qixis_read_minor());
142 /* the timestamp string contains "\n" at the end */
143 printf(" on %s", qixis_read_time(buf));
145 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
149 * Display the actual SERDES reference clocks as configured by the
150 * dip switches on the board. Note that the SWx registers could
151 * technically be set to force the reference clocks to match the
152 * values that the SERDES expects (or vice versa). For now, however,
153 * we just display both values and hope the user notices when they
156 puts("SERDES1 Reference : ");
157 sw = QIXIS_READ(brdcfg[2]);
158 clock = (sw >> 6) & 3;
159 printf("Clock1 = %sMHz ", freq[clock]);
160 clock = (sw >> 4) & 3;
161 printf("Clock2 = %sMHz", freq[clock]);
163 puts("\nSERDES2 Reference : ");
164 clock = (sw >> 2) & 3;
165 printf("Clock1 = %sMHz ", freq[clock]);
166 clock = (sw >> 0) & 3;
167 printf("Clock2 = %sMHz\n", freq[clock]);
172 bool if_board_diff_clk(void)
174 #ifdef CONFIG_TARGET_LS1088AQDS
175 u8 diff_conf = QIXIS_READ(brdcfg[11]);
176 return diff_conf & 0x40;
178 u8 diff_conf = QIXIS_READ(dutcfg[11]);
179 return diff_conf & 0x80;
183 unsigned long get_board_sys_clk(void)
185 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
187 switch (sysclk_conf & 0x0f) {
188 case QIXIS_SYSCLK_83:
190 case QIXIS_SYSCLK_100:
192 case QIXIS_SYSCLK_125:
194 case QIXIS_SYSCLK_133:
196 case QIXIS_SYSCLK_150:
198 case QIXIS_SYSCLK_160:
200 case QIXIS_SYSCLK_166:
207 unsigned long get_board_ddr_clk(void)
209 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
211 if (if_board_diff_clk())
212 return get_board_sys_clk();
213 switch ((ddrclk_conf & 0x30) >> 4) {
214 case QIXIS_DDRCLK_100:
216 case QIXIS_DDRCLK_125:
218 case QIXIS_DDRCLK_133:
225 int select_i2c_ch_pca9547(u8 ch)
229 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
231 puts("PCA: failed to select proper channel\n");
238 void board_retimer_init(void)
242 /* Retimer is connected to I2C1_CH5 */
243 select_i2c_ch_pca9547(I2C_MUX_CH5);
245 /* Access to Control/Shared register */
247 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
249 /* Read device revision and ID */
250 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
251 debug("Retimer version id = 0x%x\n", reg);
253 /* Enable Broadcast. All writes target all channel register sets */
255 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
257 /* Reset Channel Registers */
258 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
260 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
262 /* Set data rate as 10.3125 Gbps */
264 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
266 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
268 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
270 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
272 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
274 /* Select VCO Divider to full rate (000) */
275 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
278 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
280 #ifdef CONFIG_TARGET_LS1088AQDS
281 /* Retimer is connected to I2C1_CH5 */
282 select_i2c_ch_pca9547(I2C_MUX_CH5);
284 /* Access to Control/Shared register */
286 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
288 /* Read device revision and ID */
289 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
290 debug("Retimer version id = 0x%x\n", reg);
292 /* Enable Broadcast. All writes target all channel register sets */
294 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
296 /* Reset Channel Registers */
297 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
299 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
301 /* Set data rate as 10.3125 Gbps */
303 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
305 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
307 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
309 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
311 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
313 /* Select VCO Divider to full rate (000) */
314 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
317 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
319 /*return the default channel*/
320 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
323 #ifdef CONFIG_MISC_INIT_R
324 int misc_init_r(void)
326 #ifdef CONFIG_TARGET_LS1088ARDB
329 if (hwconfig("esdhc-force-sd")) {
330 brdcfg5 = QIXIS_READ(brdcfg[5]);
331 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
332 brdcfg5 |= BRDCFG5_FORCE_SD;
333 QIXIS_WRITE(brdcfg[5], brdcfg5);
340 int i2c_multiplexer_select_vid_channel(u8 channel)
342 return select_i2c_ch_pca9547(channel);
345 #ifdef CONFIG_TARGET_LS1088AQDS
346 /* read the current value(SVDD) of the LTM Regulator Voltage */
347 int get_serdes_volt(void)
350 u8 chan = PWM_CHANNEL0;
352 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
353 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
354 PMBUS_CMD_PAGE, 1, &chan, 1);
356 printf("VID: failed to select VDD Page 0\n");
360 /* Read the output voltage using PMBus command READ_VOUT */
361 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
362 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
364 printf("VID: failed to read the volatge\n");
371 int set_serdes_volt(int svdd)
374 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
375 svdd & 0xFF, (svdd & 0xFF00) >> 8};
377 /* Write the desired voltage code to the SVDD regulator */
378 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
379 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
381 printf("VID: I2C failed to write to the volatge regulator\n");
385 /* Wait for the volatge to get to the desired value */
387 vdd_last = get_serdes_volt();
389 printf("VID: Couldn't read sensor abort VID adjust\n");
392 } while (vdd_last != svdd);
397 int get_serdes_volt(void)
402 int set_serdes_volt(int svdd)
407 printf("SVDD changing of RDB\n");
409 /* Read the BRDCFG54 via CLPD */
410 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
411 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
413 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
417 brdcfg4 = brdcfg4 | 0x08;
419 /* Write to the BRDCFG4 */
420 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
421 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
423 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
427 /* Wait for the volatge to get to the desired value */
434 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
435 int board_adjust_vdd(int vdd)
439 debug("%s: vdd = %d\n", __func__, vdd);
441 /* Special settings to be performed when voltage is 900mV */
443 ret = setup_serdes_volt(vdd);
455 init_final_memctl_regs();
456 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
457 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
460 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
461 board_retimer_init();
463 #ifdef CONFIG_ENV_IS_NOWHERE
464 gd->env_addr = (ulong)&default_environment[0];
467 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
468 /* invert AQR105 IRQ pins polarity */
469 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
472 #ifdef CONFIG_FSL_CAAM
475 #ifdef CONFIG_FSL_LS_PPA
481 void detail_board_ddr_info(void)
484 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
488 #if defined(CONFIG_ARCH_MISC_INIT)
489 int arch_misc_init(void)
495 #ifdef CONFIG_FSL_MC_ENET
496 void fdt_fixup_board_enet(void *fdt)
500 offset = fdt_path_offset(fdt, "/fsl-mc");
503 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
506 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
511 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
512 fdt_status_okay(fdt, offset);
514 fdt_status_fail(fdt, offset);
518 #ifdef CONFIG_OF_BOARD_SETUP
519 void fsl_fdt_fixup_flash(void *fdt)
524 * IFC-NOR and QSPI are muxed on SoC.
525 * So disable IFC node in dts if QSPI is enabled or
526 * disable QSPI node in dts in case QSPI is not enabled.
529 #ifdef CONFIG_FSL_QSPI
530 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
533 offset = fdt_path_offset(fdt, "/ifc/nor");
535 offset = fdt_path_offset(fdt, "/soc/quadspi");
538 offset = fdt_path_offset(fdt, "/quadspi");
543 fdt_status_disabled(fdt, offset);
546 int ft_board_setup(void *blob, bd_t *bd)
549 u64 base[CONFIG_NR_DRAM_BANKS];
550 u64 size[CONFIG_NR_DRAM_BANKS];
552 ft_cpu_setup(blob, bd);
554 /* fixup DT for the two GPP DDR banks */
555 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
556 base[i] = gd->bd->bi_dram[i].start;
557 size[i] = gd->bd->bi_dram[i].size;
560 #ifdef CONFIG_RESV_RAM
561 /* reduce size if reserved memory is within this bank */
562 if (gd->arch.resv_ram >= base[0] &&
563 gd->arch.resv_ram < base[0] + size[0])
564 size[0] = gd->arch.resv_ram - base[0];
565 else if (gd->arch.resv_ram >= base[1] &&
566 gd->arch.resv_ram < base[1] + size[1])
567 size[1] = gd->arch.resv_ram - base[1];
570 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
572 fsl_fdt_fixup_flash(blob);
574 #ifdef CONFIG_FSL_MC_ENET
575 fdt_fixup_board_enet(blob);
576 err = fsl_mc_ldpaa_exit(bd);
584 #endif /* defined(CONFIG_SPL_BUILD) */