4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <fsl-mc/ldpaa_wriop.h>
20 #include "../common/qixis.h"
22 #include "ls1088a_qixis.h"
24 #ifdef CONFIG_FSL_MC_ENET
28 /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
29 * Bank 1 -> Lanes A, B, C, D,
30 * Bank 2 -> Lanes A,B, C, D,
33 /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
34 * means that the mapping must be determined dynamically, or that the lane
35 * maps to something other than a board slot.
38 static u8 lane_to_slot_fsm1[] = {
39 0, 0, 0, 0, 0, 0, 0, 0
42 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
46 static int xqsgii_riser_phy_addr[] = {
47 XQSGMII_CARD_PHY1_PORT0_ADDR,
48 XQSGMII_CARD_PHY2_PORT0_ADDR,
49 XQSGMII_CARD_PHY3_PORT0_ADDR,
50 XQSGMII_CARD_PHY4_PORT0_ADDR,
51 XQSGMII_CARD_PHY3_PORT2_ADDR,
52 XQSGMII_CARD_PHY1_PORT2_ADDR,
53 XQSGMII_CARD_PHY4_PORT2_ADDR,
54 XQSGMII_CARD_PHY2_PORT2_ADDR,
57 static int sgmii_riser_phy_addr[] = {
58 SGMII_CARD_PORT1_PHY_ADDR,
59 SGMII_CARD_PORT2_PHY_ADDR,
60 SGMII_CARD_PORT3_PHY_ADDR,
61 SGMII_CARD_PORT4_PHY_ADDR,
64 /* Slot2 does not have EMI connections */
70 static const char * const mdio_names[] = {
74 DEFAULT_WRIOP_MDIO2_NAME,
77 struct ls1088a_qds_mdio {
79 struct mii_dev *realbus;
82 static void sgmii_configure_repeater(int dpmac)
88 const char *dev = "LS1088A_QDS_MDIO2";
89 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
93 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
94 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
95 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
96 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
98 /* Set I2c to Slot 1 */
99 i2c_write(0x77, 0, 0, &a, 1);
103 i2c_phy_addr = i2c_addr[1];
107 i2c_phy_addr = i2c_addr[0];
111 i2c_phy_addr = i2c_addr[3];
115 i2c_phy_addr = i2c_addr[2];
120 /* Check the PHY status */
121 ret = miiphy_set_current_dev(dev);
125 bus = mdio_get_current_dev();
126 debug("Reading from bus %s\n", bus->name);
128 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
133 ret = miiphy_read(dev, phy_addr, 0x11, &value);
139 if ((value & 0xfff) == 0x401) {
140 miiphy_write(dev, phy_addr, 0x1f, 0);
141 printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
145 for (i = 0; i < 4; i++) {
146 for (j = 0; j < 4; j++) {
148 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
150 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
152 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
154 i2c_write(i2c_phy_addr, 0xf, 1,
156 i2c_write(i2c_phy_addr, 0x11, 1,
159 i2c_write(i2c_phy_addr, 0x16, 1,
161 i2c_write(i2c_phy_addr, 0x18, 1,
165 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
167 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
169 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
171 ret = miiphy_read(dev, phy_addr, 0x11, &value);
176 ret = miiphy_read(dev, phy_addr, 0x11, &value);
180 if ((value & 0xfff) == 0x401) {
181 printf("DPMAC %d :PHY is configured ",
183 printf("after setting repeater 0x%x\n",
188 printf("DPMAC %d :PHY is failed to ",
190 printf("configure the repeater 0x%x\n", value);
194 miiphy_write(dev, phy_addr, 0x1f, 0);
197 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
201 static void qsgmii_configure_repeater(int dpmac)
205 int i2c_phy_addr = 0;
207 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
209 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
210 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
211 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
212 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
214 const char *dev = mdio_names[EMI1_SLOT1];
216 unsigned short value;
218 /* Set I2c to Slot 1 */
219 i2c_write(0x77, 0, 0, &a, 1);
226 i2c_phy_addr = i2c_addr[2];
234 i2c_phy_addr = i2c_addr[3];
239 /* Check the PHY status */
240 ret = miiphy_set_current_dev(dev);
241 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
243 ret = miiphy_read(dev, phy_addr, 0x11, &value);
245 ret = miiphy_read(dev, phy_addr, 0x11, &value);
247 if ((value & 0xf) == 0xf) {
248 miiphy_write(dev, phy_addr, 0x1f, 0);
249 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
253 for (i = 0; i < 4; i++) {
254 for (j = 0; j < 4; j++) {
256 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
258 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
260 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
262 i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
263 i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
265 i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
266 i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
269 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
271 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
273 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
275 ret = miiphy_read(dev, phy_addr, 0x11, &value);
279 ret = miiphy_read(dev, phy_addr, 0x11, &value);
283 if ((value & 0xf) == 0xf) {
284 miiphy_write(dev, phy_addr, 0x1f, 0);
285 printf("DPMAC %d :PHY is ..... Configured\n",
292 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
296 static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
298 return mdio_names[muxval];
301 struct mii_dev *mii_dev_for_muxval(u8 muxval)
304 const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
307 printf("No bus for muxval %x\n", muxval);
311 bus = miiphy_get_dev_by_name(name);
314 printf("No bus by name %s\n", name);
321 static void ls1088a_qds_enable_SFP_TX(u8 muxval)
325 brdcfg9 = QIXIS_READ(brdcfg[9]);
326 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
327 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
328 QIXIS_WRITE(brdcfg[9], brdcfg9);
331 static void ls1088a_qds_mux_mdio(u8 muxval)
336 brdcfg4 = QIXIS_READ(brdcfg[4]);
337 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
338 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
339 QIXIS_WRITE(brdcfg[4], brdcfg4);
343 static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
344 int devad, int regnum)
346 struct ls1088a_qds_mdio *priv = bus->priv;
348 ls1088a_qds_mux_mdio(priv->muxval);
350 return priv->realbus->read(priv->realbus, addr, devad, regnum);
353 static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
354 int regnum, u16 value)
356 struct ls1088a_qds_mdio *priv = bus->priv;
358 ls1088a_qds_mux_mdio(priv->muxval);
360 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
363 static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
365 struct ls1088a_qds_mdio *priv = bus->priv;
367 return priv->realbus->reset(priv->realbus);
370 static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
372 struct ls1088a_qds_mdio *pmdio;
373 struct mii_dev *bus = mdio_alloc();
376 printf("Failed to allocate ls1088a_qds MDIO bus\n");
380 pmdio = malloc(sizeof(*pmdio));
382 printf("Failed to allocate ls1088a_qds private data\n");
387 bus->read = ls1088a_qds_mdio_read;
388 bus->write = ls1088a_qds_mdio_write;
389 bus->reset = ls1088a_qds_mdio_reset;
390 sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
392 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
394 if (!pmdio->realbus) {
395 printf("No bus with name %s\n", realbusname);
401 pmdio->muxval = muxval;
404 return mdio_register(bus);
408 * Initialize the dpmac_info array.
411 static void initialize_dpmac_to_slot(void)
413 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
414 u32 serdes1_prtcl, cfg;
416 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
417 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
418 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
419 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
421 switch (serdes1_prtcl) {
423 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
425 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
426 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
427 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
428 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
432 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
434 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
435 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
436 lane_to_slot_fsm1[2] = EMI_NONE;
437 lane_to_slot_fsm1[3] = EMI_NONE;
440 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
442 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
443 lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
444 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
445 lane_to_slot_fsm1[3] = EMI_NONE;
448 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
450 lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
451 lane_to_slot_fsm1[1] = EMI_NONE;
452 lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
453 lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
457 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
458 __func__, serdes1_prtcl);
463 void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
466 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
467 u32 serdes1_prtcl, cfg;
469 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
470 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
471 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
472 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
475 char *env_hwconfig = env_get("hwconfig");
477 if (hwconfig_f("xqsgmii", env_hwconfig))
478 riser_phy_addr = &xqsgii_riser_phy_addr[0];
480 riser_phy_addr = &sgmii_riser_phy_addr[0];
482 switch (serdes1_prtcl) {
489 wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
492 wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
495 wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
498 wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
501 printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
506 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
507 __func__, serdes1_prtcl);
510 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
511 bus = mii_dev_for_muxval(EMI1_SLOT1);
512 wriop_set_mdio(dpmac_id, bus);
515 void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
518 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
519 u32 serdes1_prtcl, cfg;
521 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
522 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
523 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
524 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
526 switch (serdes1_prtcl) {
534 wriop_set_phy_address(dpmac_id, dpmac_id + 9);
540 wriop_set_phy_address(dpmac_id, dpmac_id + 1);
544 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
545 bus = mii_dev_for_muxval(EMI1_SLOT1);
546 wriop_set_mdio(dpmac_id, bus);
549 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
555 void ls1088a_handle_phy_interface_xsgmii(int i)
557 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
558 u32 serdes1_prtcl, cfg;
560 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
561 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
562 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
563 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
565 switch (serdes1_prtcl) {
569 wriop_set_phy_address(i, i + 26);
570 ls1088a_qds_enable_SFP_TX(SFP_TX);
573 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
579 static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
581 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
582 u32 serdes1_prtcl, cfg;
585 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
586 FSL_CHASSIS3_SRDS1_PRTCL_MASK;
587 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
588 serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
592 wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR);
593 dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
594 bus = mii_dev_for_muxval(EMI1_RGMII1);
595 wriop_set_mdio(dpmac_id, bus);
598 wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR);
599 dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
600 bus = mii_dev_for_muxval(EMI1_RGMII2);
601 wriop_set_mdio(dpmac_id, bus);
604 printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
611 int board_eth_init(bd_t *bis)
614 #ifdef CONFIG_FSL_MC_ENET
615 struct memac_mdio_info *memac_mdio0_info;
616 char *env_hwconfig = env_get("hwconfig");
618 initialize_dpmac_to_slot();
620 memac_mdio0_info = (struct memac_mdio_info *)malloc(
621 sizeof(struct memac_mdio_info));
622 memac_mdio0_info->regs =
623 (struct memac_mdio_controller *)
624 CONFIG_SYS_FSL_WRIOP1_MDIO1;
625 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
627 /* Register the real MDIO1 bus */
628 fm_memac_mdio_init(bis, memac_mdio0_info);
629 /* Register the muxing front-ends to the MDIO buses */
630 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
631 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
632 ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
634 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
635 switch (wriop_get_enet_if(i)) {
636 case PHY_INTERFACE_MODE_RGMII:
637 case PHY_INTERFACE_MODE_RGMII_ID:
638 ls1088a_handle_phy_interface_rgmii(i);
640 case PHY_INTERFACE_MODE_QSGMII:
641 ls1088a_handle_phy_interface_qsgmii(i);
643 case PHY_INTERFACE_MODE_SGMII:
644 ls1088a_handle_phy_interface_sgmii(i);
646 case PHY_INTERFACE_MODE_XGMII:
647 ls1088a_handle_phy_interface_xsgmii(i);
657 error = cpu_eth_init(bis);
659 if (hwconfig_f("xqsgmii", env_hwconfig)) {
660 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
661 switch (wriop_get_enet_if(i)) {
662 case PHY_INTERFACE_MODE_QSGMII:
663 qsgmii_configure_repeater(i);
665 case PHY_INTERFACE_MODE_SGMII:
666 sgmii_configure_repeater(i);
677 error = pci_eth_init(bis);
681 #if defined(CONFIG_RESET_PHY_R)
686 #endif /* CONFIG_RESET_PHY_R */