2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ppa.h>
14 #include <asm/arch/soc.h>
21 #include <fsl_esdhc.h>
22 #include <power/mc34vr500_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 int board_early_init_f(void)
30 fsl_lsch2_early_init_f();
35 #ifndef CONFIG_SPL_BUILD
38 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
39 u8 cfg_rcw_src1, cfg_rcw_src2;
43 puts("Board: LS1046ARDB, boot from ");
45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
47 cpld_rev_bit(&cfg_rcw_src1);
48 cfg_rcw_src = cfg_rcw_src1;
49 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
51 if (cfg_rcw_src == 0x44)
52 printf("QSPI vBank %d\n", CPLD_READ(vbank));
53 else if (cfg_rcw_src == 0x40)
56 puts("Invalid setting of SW5\n");
58 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
59 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
61 puts("SERDES Reference Clocks:\n");
62 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
63 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
70 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
72 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
73 enable_layerscape_ns_access();
76 #ifdef CONFIG_SECURE_BOOT
78 * In case of Secure Boot, the IBR configures the SMMU
79 * to allow only Secure transactions.
80 * SMMU must be reset in bypass mode.
81 * Set the ClientPD bit and Clear the USFCFG Bit
84 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
85 out_le32(SMMU_SCR0, val);
86 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
87 out_le32(SMMU_NSCR0, val);
90 #ifdef CONFIG_FSL_CAAM
94 #ifdef CONFIG_FSL_LS_PPA
98 /* invert AQR105 IRQ pins polarity */
99 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
104 int board_setup_core_volt(u32 vdd)
108 en_0v9 = (vdd == 900) ? true : false;
109 cpld_select_core_volt(en_0v9);
114 int get_serdes_volt(void)
116 return mc34vr500_get_sw_volt(SW4);
119 int set_serdes_volt(int svdd)
121 return mc34vr500_set_sw_volt(SW4, svdd);
124 int power_init_board(void)
128 ret = power_mc34vr500_init(0);
137 void config_board_mux(void)
139 #ifdef CONFIG_HAS_FSL_XHCI_USB
140 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
143 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
144 out_be32(&scfg->rcwpmuxcr0, 0x3300);
145 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
146 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
147 SCFG_USBPWRFAULT_USB3_SHIFT) |
148 (SCFG_USBPWRFAULT_DEDICATED <<
149 SCFG_USBPWRFAULT_USB2_SHIFT) |
150 (SCFG_USBPWRFAULT_SHARED <<
151 SCFG_USBPWRFAULT_USB1_SHIFT);
152 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
156 #ifdef CONFIG_MISC_INIT_R
157 int misc_init_r(void)
164 int ft_board_setup(void *blob, bd_t *bd)
166 u64 base[CONFIG_NR_DRAM_BANKS];
167 u64 size[CONFIG_NR_DRAM_BANKS];
169 /* fixup DT for the two DDR banks */
170 base[0] = gd->bd->bi_dram[0].start;
171 size[0] = gd->bd->bi_dram[0].size;
172 base[1] = gd->bd->bi_dram[1].start;
173 size[1] = gd->bd->bi_dram[1].size;
175 fdt_fixup_memory_banks(blob, base, size, 2);
176 ft_cpu_setup(blob, bd);
178 #ifdef CONFIG_SYS_DPAA_FMAN
179 fdt_fixup_fman_ethernet(blob);