board/freescale/ls1046ardb/ls1046ardb.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/ppa.h>
  14 #include <asm/arch/soc.h>
  15 #include <hwconfig.h>
  16 #include <ahci.h>
  17 #include <mmc.h>
  18 #include <scsi.h>
  19 #include <fm_eth.h>
  20 #include <fsl_csu.h>
  21 #include <fsl_esdhc.h>
  22 #include <power/mc34vr500_pmic.h>
  23 #include "cpld.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int checkboard(void)
  28 {
  29         static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
  30         u8 cfg_rcw_src1, cfg_rcw_src2;
  31         u16 cfg_rcw_src;
  32         u8 sd1refclk_sel;
  33
  34         puts("Board: LS1046ARDB, boot from ");
  35
  36         cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
  37         cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
  38         cpld_rev_bit(&cfg_rcw_src1);
  39         cfg_rcw_src = cfg_rcw_src1;
  40         cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
  41
  42         if (cfg_rcw_src == 0x44)
  43                 printf("QSPI vBank %d\n", CPLD_READ(vbank));
  44         else if (cfg_rcw_src == 0x40)
  45                 puts("SD\n");
  46         else
  47                 puts("Invalid setting of SW5\n");
  48
  49         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
  50                CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
  51
  52         puts("SERDES Reference Clocks:\n");
  53         sd1refclk_sel = CPLD_READ(sd1refclk_sel);
  54         printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
  55
  56         return 0;
  57 }
  58
  59 int board_early_init_f(void)
  60 {
  61         fsl_lsch2_early_init_f();
  62
  63         return 0;
  64 }
  65
  66 int board_init(void)
  67 {
  68         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  69
  70 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  71         enable_layerscape_ns_access();
  72 #endif
  73
  74 #ifdef CONFIG_FSL_LS_PPA
  75         ppa_init();
  76 #endif
  77
  78         /* invert AQR105 IRQ pins polarity */
  79         out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
  80
  81         return 0;
  82 }
  83
  84 int board_setup_core_volt(u32 vdd)
  85 {
  86         bool en_0v9;
  87
  88         en_0v9 = (vdd == 900) ? true : false;
  89         cpld_select_core_volt(en_0v9);
  90
  91         return 0;
  92 }
  93
  94 int get_serdes_volt(void)
  95 {
  96         return mc34vr500_get_sw_volt(SW4);
  97 }
  98
  99 int set_serdes_volt(int svdd)
 100 {
 101         return mc34vr500_set_sw_volt(SW4, svdd);
 102 }
 103
 104 int power_init_board(void)
 105 {
 106         int ret;
 107
 108         ret = power_mc34vr500_init(0);
 109         if (ret)
 110                 return ret;
 111
 112         setup_chip_volt();
 113
 114         return 0;
 115 }
 116
 117 void config_board_mux(void)
 118 {
 119 #ifdef CONFIG_HAS_FSL_XHCI_USB
 120         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 121         u32 usb_pwrfault;
 122
 123         /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
 124         out_be32(&scfg->rcwpmuxcr0, 0x3300);
 125         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 126         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 127                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 128                         (SCFG_USBPWRFAULT_DEDICATED <<
 129                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 130                         (SCFG_USBPWRFAULT_SHARED <<
 131                         SCFG_USBPWRFAULT_USB1_SHIFT);
 132         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 133 #endif
 134 }
 135
 136 #ifdef CONFIG_MISC_INIT_R
 137 int misc_init_r(void)
 138 {
 139         config_board_mux();
 140         return 0;
 141 }
 142 #endif
 143
 144 int ft_board_setup(void *blob, bd_t *bd)
 145 {
 146         u64 base[CONFIG_NR_DRAM_BANKS];
 147         u64 size[CONFIG_NR_DRAM_BANKS];
 148
 149         /* fixup DT for the two DDR banks */
 150         base[0] = gd->bd->bi_dram[0].start;
 151         size[0] = gd->bd->bi_dram[0].size;
 152         base[1] = gd->bd->bi_dram[1].start;
 153         size[1] = gd->bd->bi_dram[1].size;
 154
 155         fdt_fixup_memory_banks(blob, base, size, 2);
 156         ft_cpu_setup(blob, bd);
 157
 158 #ifdef CONFIG_SYS_DPAA_FMAN
 159         fdt_fixup_fman_ethernet(blob);
 160 #endif
 161
 162         return 0;
 163 }