1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
10 #include <asm/global_data.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ppa.h>
15 #include <asm/arch/soc.h>
16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
23 #include <fsl_esdhc.h>
24 #include <power/mc34vr500_pmic.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 int board_early_init_f(void)
32 fsl_lsch2_early_init_f();
37 #ifndef CONFIG_SPL_BUILD
40 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
41 u8 cfg_rcw_src1, cfg_rcw_src2;
45 puts("Board: LS1046ARDB, boot from ");
47 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
48 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
49 cpld_rev_bit(&cfg_rcw_src1);
50 cfg_rcw_src = cfg_rcw_src1;
51 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
53 if (cfg_rcw_src == 0x44)
54 printf("QSPI vBank %d\n", CPLD_READ(vbank));
55 else if (cfg_rcw_src == 0x40)
58 puts("Invalid setting of SW5\n");
60 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
61 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
63 puts("SERDES Reference Clocks:\n");
64 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
65 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
72 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
74 #ifdef CONFIG_NXP_ESBC
76 * In case of Secure Boot, the IBR configures the SMMU
77 * to allow only Secure transactions.
78 * SMMU must be reset in bypass mode.
79 * Set the ClientPD bit and Clear the USFCFG Bit
82 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
83 out_le32(SMMU_SCR0, val);
84 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
85 out_le32(SMMU_NSCR0, val);
88 #ifdef CONFIG_FSL_CAAM
92 #ifdef CONFIG_FSL_LS_PPA
96 /* invert AQR105 IRQ pins polarity */
97 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
102 int board_setup_core_volt(u32 vdd)
106 en_0v9 = (vdd == 900) ? true : false;
107 cpld_select_core_volt(en_0v9);
112 int get_serdes_volt(void)
114 return mc34vr500_get_sw_volt(SW4);
117 int set_serdes_volt(int svdd)
119 return mc34vr500_set_sw_volt(SW4, svdd);
122 int power_init_board(void)
126 ret = power_mc34vr500_init(0);
135 void config_board_mux(void)
137 #ifdef CONFIG_HAS_FSL_XHCI_USB
138 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
141 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
142 out_be32(&scfg->rcwpmuxcr0, 0x3300);
143 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
144 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
145 SCFG_USBPWRFAULT_USB3_SHIFT) |
146 (SCFG_USBPWRFAULT_DEDICATED <<
147 SCFG_USBPWRFAULT_USB2_SHIFT) |
148 (SCFG_USBPWRFAULT_SHARED <<
149 SCFG_USBPWRFAULT_USB1_SHIFT);
150 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
154 #ifdef CONFIG_MISC_INIT_R
155 int misc_init_r(void)
162 int ft_board_setup(void *blob, struct bd_info *bd)
164 u64 base[CONFIG_NR_DRAM_BANKS];
165 u64 size[CONFIG_NR_DRAM_BANKS];
167 /* fixup DT for the two DDR banks */
168 base[0] = gd->bd->bi_dram[0].start;
169 size[0] = gd->bd->bi_dram[0].size;
170 base[1] = gd->bd->bi_dram[1].start;
171 size[1] = gd->bd->bi_dram[1].size;
173 fdt_fixup_memory_banks(blob, base, size, 2);
174 ft_cpu_setup(blob, bd);
176 #ifdef CONFIG_SYS_DPAA_FMAN
177 #ifndef CONFIG_DM_ETH
178 fdt_fixup_fman_ethernet(blob);
182 fdt_fixup_icid(blob);