board/freescale/ls1046ardb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <fsl_ddr_sdram.h>
   8 #include <fsl_ddr_dimm_params.h>
   9 #include <asm/global_data.h>
  10 #include "ddr.h"
  11 #ifdef CONFIG_FSL_DEEP_SLEEP
  12 #include <fsl_sleep.h>
  13 #endif
  14 #include <log.h>
  15 #include <asm/arch/clock.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 void fsl_ddr_board_options(memctl_options_t *popts,
  20                            dimm_params_t *pdimm,
  21                            unsigned int ctrl_num)
  22 {
  23         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  24         ulong ddr_freq;
  25
  26         if (ctrl_num > 1) {
  27                 printf("Not supported controller number %d\n", ctrl_num);
  28                 return;
  29         }
  30         if (!pdimm->n_ranks)
  31                 return;
  32
  33         if (popts->registered_dimm_en)
  34                 pbsp = rdimms[0];
  35         else
  36                 pbsp = udimms[0];
  37
  38         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  39          * freqency and n_banks specified in board_specific_parameters table.
  40          */
  41         ddr_freq = get_ddr_freq(0) / 1000000;
  42         while (pbsp->datarate_mhz_high) {
  43                 if (pbsp->n_ranks == pdimm->n_ranks) {
  44                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  45                                 popts->clk_adjust = pbsp->clk_adjust;
  46                                 popts->wrlvl_start = pbsp->wrlvl_start;
  47                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  48                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  49                                 goto found;
  50                         }
  51                         pbsp_highest = pbsp;
  52                 }
  53                 pbsp++;
  54         }
  55
  56         if (pbsp_highest) {
  57                 printf("Error: board specific timing not found for %lu MT/s\n",
  58                        ddr_freq);
  59                 printf("Trying to use the highest speed (%u) parameters\n",
  60                        pbsp_highest->datarate_mhz_high);
  61                 popts->clk_adjust = pbsp_highest->clk_adjust;
  62                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  63                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  64                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  65         } else {
  66                 panic("DIMM is not supported by this board");
  67         }
  68 found:
  69         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  70               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  71
  72         popts->data_bus_width = 0;      /* 64-bit data bus */
  73         popts->bstopre = 0;             /* enable auto precharge */
  74
  75         /*
  76          * Factors to consider for half-strength driver enable:
  77          *      - number of DIMMs installed
  78          */
  79         popts->half_strength_driver_enable = 0;
  80         /*
  81          * Write leveling override
  82          */
  83         popts->wrlvl_override = 1;
  84         popts->wrlvl_sample = 0xf;
  85
  86         /*
  87          * Rtt and Rtt_WR override
  88          */
  89         popts->rtt_override = 0;
  90
  91         /* Enable ZQ calibration */
  92         popts->zq_en = 1;
  93
  94         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  95         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  96                           DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  97
  98         /* optimize cpo for erratum A-009942 */
  99         popts->cpo_sample = 0x61;
 100 }
 101
 102 #ifdef CONFIG_TFABOOT
 103 int fsl_initdram(void)
 104 {
 105         gd->ram_size = tfa_get_dram_size();
 106
 107         if (!gd->ram_size)
 108                 gd->ram_size = fsl_ddr_sdram_size();
 109
 110         return 0;
 111 }
 112 #else
 113 int fsl_initdram(void)
 114 {
 115         phys_size_t dram_size;
 116
 117 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 118         gd->ram_size = fsl_ddr_sdram_size();
 119
 120         return 0;
 121 #else
 122         puts("Initializing DDR....using SPD\n");
 123
 124         dram_size = fsl_ddr_sdram();
 125 #endif
 126
 127         erratum_a008850_post();
 128
 129         gd->ram_size = dram_size;
 130
 131         return 0;
 132 }
 133 #endif