board/freescale/ls1046aqds/ls1046aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/fsl_serdes.h>
  15 #include <asm/arch/ppa.h>
  16 #include <asm/arch/fdt.h>
  17 #include <asm/arch/mmu.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/soc.h>
  20 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  21 #include <ahci.h>
  22 #include <hwconfig.h>
  23 #include <mmc.h>
  24 #include <scsi.h>
  25 #include <fm_eth.h>
  26 #include <fsl_csu.h>
  27 #include <fsl_esdhc.h>
  28 #include <fsl_ifc.h>
  29 #include <fsl_sec.h>
  30 #include <spl.h>
  31
  32 #include "../common/vid.h"
  33 #include "../common/qixis.h"
  34 #include "ls1046aqds_qixis.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #ifdef CONFIG_TFABOOT
  39 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  40         {
  41                 "nor0",
  42                 CONFIG_SYS_NOR0_CSPR,
  43                 CONFIG_SYS_NOR0_CSPR_EXT,
  44                 CONFIG_SYS_NOR_AMASK,
  45                 CONFIG_SYS_NOR_CSOR,
  46                 {
  47                         CONFIG_SYS_NOR_FTIM0,
  48                         CONFIG_SYS_NOR_FTIM1,
  49                         CONFIG_SYS_NOR_FTIM2,
  50                         CONFIG_SYS_NOR_FTIM3
  51                 },
  52
  53         },
  54         {
  55                 "nor1",
  56                 CONFIG_SYS_NOR1_CSPR,
  57                 CONFIG_SYS_NOR1_CSPR_EXT,
  58                 CONFIG_SYS_NOR_AMASK,
  59                 CONFIG_SYS_NOR_CSOR,
  60                 {
  61                         CONFIG_SYS_NOR_FTIM0,
  62                         CONFIG_SYS_NOR_FTIM1,
  63                         CONFIG_SYS_NOR_FTIM2,
  64                         CONFIG_SYS_NOR_FTIM3
  65                 },
  66         },
  67         {
  68                 "nand",
  69                 CONFIG_SYS_NAND_CSPR,
  70                 CONFIG_SYS_NAND_CSPR_EXT,
  71                 CONFIG_SYS_NAND_AMASK,
  72                 CONFIG_SYS_NAND_CSOR,
  73                 {
  74                         CONFIG_SYS_NAND_FTIM0,
  75                         CONFIG_SYS_NAND_FTIM1,
  76                         CONFIG_SYS_NAND_FTIM2,
  77                         CONFIG_SYS_NAND_FTIM3
  78                 },
  79         },
  80         {
  81                 "fpga",
  82                 CONFIG_SYS_FPGA_CSPR,
  83                 CONFIG_SYS_FPGA_CSPR_EXT,
  84                 CONFIG_SYS_FPGA_AMASK,
  85                 CONFIG_SYS_FPGA_CSOR,
  86                 {
  87                         CONFIG_SYS_FPGA_FTIM0,
  88                         CONFIG_SYS_FPGA_FTIM1,
  89                         CONFIG_SYS_FPGA_FTIM2,
  90                         CONFIG_SYS_FPGA_FTIM3
  91                 },
  92         }
  93 };
  94
  95 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  96         {
  97                 "nand",
  98                 CONFIG_SYS_NAND_CSPR,
  99                 CONFIG_SYS_NAND_CSPR_EXT,
 100                 CONFIG_SYS_NAND_AMASK,
 101                 CONFIG_SYS_NAND_CSOR,
 102                 {
 103                         CONFIG_SYS_NAND_FTIM0,
 104                         CONFIG_SYS_NAND_FTIM1,
 105                         CONFIG_SYS_NAND_FTIM2,
 106                         CONFIG_SYS_NAND_FTIM3
 107                 },
 108         },
 109         {
 110                 "nor0",
 111                 CONFIG_SYS_NOR0_CSPR,
 112                 CONFIG_SYS_NOR0_CSPR_EXT,
 113                 CONFIG_SYS_NOR_AMASK,
 114                 CONFIG_SYS_NOR_CSOR,
 115                 {
 116                         CONFIG_SYS_NOR_FTIM0,
 117                         CONFIG_SYS_NOR_FTIM1,
 118                         CONFIG_SYS_NOR_FTIM2,
 119                         CONFIG_SYS_NOR_FTIM3
 120                 },
 121         },
 122         {
 123                 "nor1",
 124                 CONFIG_SYS_NOR1_CSPR,
 125                 CONFIG_SYS_NOR1_CSPR_EXT,
 126                 CONFIG_SYS_NOR_AMASK,
 127                 CONFIG_SYS_NOR_CSOR,
 128                 {
 129                         CONFIG_SYS_NOR_FTIM0,
 130                         CONFIG_SYS_NOR_FTIM1,
 131                         CONFIG_SYS_NOR_FTIM2,
 132                         CONFIG_SYS_NOR_FTIM3
 133                 },
 134         },
 135         {
 136                 "fpga",
 137                 CONFIG_SYS_FPGA_CSPR,
 138                 CONFIG_SYS_FPGA_CSPR_EXT,
 139                 CONFIG_SYS_FPGA_AMASK,
 140                 CONFIG_SYS_FPGA_CSOR,
 141                 {
 142                         CONFIG_SYS_FPGA_FTIM0,
 143                         CONFIG_SYS_FPGA_FTIM1,
 144                         CONFIG_SYS_FPGA_FTIM2,
 145                         CONFIG_SYS_FPGA_FTIM3
 146                 },
 147         }
 148 };
 149
 150 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 151 {
 152         enum boot_src src = get_boot_src();
 153
 154         if (src == BOOT_SOURCE_IFC_NAND)
 155                 regs_info->regs = ifc_cfg_nand_boot;
 156         else
 157                 regs_info->regs = ifc_cfg_nor_boot;
 158         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 159 }
 160
 161 #endif
 162
 163 enum {
 164         MUX_TYPE_GPIO,
 165 };
 166
 167 int checkboard(void)
 168 {
 169 #ifdef CONFIG_TFABOOT
 170         enum boot_src src = get_boot_src();
 171 #endif
 172         char buf[64];
 173 #ifndef CONFIG_SD_BOOT
 174         u8 sw;
 175 #endif
 176
 177         puts("Board: LS1046AQDS, boot from ");
 178
 179 #ifdef CONFIG_TFABOOT
 180         if (src == BOOT_SOURCE_SD_MMC)
 181                 puts("SD\n");
 182         else {
 183 #endif
 184
 185 #ifdef CONFIG_SD_BOOT
 186         puts("SD\n");
 187 #else
 188         sw = QIXIS_READ(brdcfg[0]);
 189         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 190
 191         if (sw < 0x8)
 192                 printf("vBank: %d\n", sw);
 193         else if (sw == 0x8)
 194                 puts("PromJet\n");
 195         else if (sw == 0x9)
 196                 puts("NAND\n");
 197         else if (sw == 0xF)
 198                 printf("QSPI\n");
 199         else
 200                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 201 #endif
 202
 203 #ifdef CONFIG_TFABOOT
 204         }
 205 #endif
 206         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 207                QIXIS_READ(id), QIXIS_READ(arch));
 208
 209         printf("FPGA:  v%d (%s), build %d\n",
 210                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 211                (int)qixis_read_minor());
 212
 213         return 0;
 214 }
 215
 216 bool if_board_diff_clk(void)
 217 {
 218         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 219
 220         return diff_conf & 0x40;
 221 }
 222
 223 unsigned long get_board_sys_clk(void)
 224 {
 225         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 226
 227         switch (sysclk_conf & 0x0f) {
 228         case QIXIS_SYSCLK_64:
 229                 return 64000000;
 230         case QIXIS_SYSCLK_83:
 231                 return 83333333;
 232         case QIXIS_SYSCLK_100:
 233                 return 100000000;
 234         case QIXIS_SYSCLK_125:
 235                 return 125000000;
 236         case QIXIS_SYSCLK_133:
 237                 return 133333333;
 238         case QIXIS_SYSCLK_150:
 239                 return 150000000;
 240         case QIXIS_SYSCLK_160:
 241                 return 160000000;
 242         case QIXIS_SYSCLK_166:
 243                 return 166666666;
 244         }
 245
 246         return 66666666;
 247 }
 248
 249 unsigned long get_board_ddr_clk(void)
 250 {
 251         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 252
 253         if (if_board_diff_clk())
 254                 return get_board_sys_clk();
 255         switch ((ddrclk_conf & 0x30) >> 4) {
 256         case QIXIS_DDRCLK_100:
 257                 return 100000000;
 258         case QIXIS_DDRCLK_125:
 259                 return 125000000;
 260         case QIXIS_DDRCLK_133:
 261                 return 133333333;
 262         }
 263
 264         return 66666666;
 265 }
 266
 267 #ifdef CONFIG_LPUART
 268 u32 get_lpuart_clk(void)
 269 {
 270         return gd->bus_clk;
 271 }
 272 #endif
 273
 274 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 275 {
 276         int ret;
 277 #ifdef CONFIG_DM_I2C
 278         struct udevice *dev;
 279
 280         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 281                                       1, &dev);
 282         if (ret) {
 283                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 284                        bus_num);
 285                 return ret;
 286         }
 287         ret = dm_i2c_write(dev, 0, &ch, 1);
 288 #else
 289         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 290 #endif
 291         if (ret) {
 292                 puts("PCA: failed to select proper channel\n");
 293                 return ret;
 294         }
 295
 296         return 0;
 297 }
 298
 299 int dram_init(void)
 300 {
 301         /*
 302          * When resuming from deep sleep, the I2C channel may not be
 303          * in the default channel. So, switch to the default channel
 304          * before accessing DDR SPD.
 305          *
 306          * PCA9547 mount on I2C1 bus
 307          */
 308         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 309         fsl_initdram();
 310 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 311         defined(CONFIG_SPL_BUILD)
 312         /* This will break-before-make MMU for DDR */
 313         update_early_mmu_table();
 314 #endif
 315
 316         return 0;
 317 }
 318
 319 int i2c_multiplexer_select_vid_channel(u8 channel)
 320 {
 321         return select_i2c_ch_pca9547(channel, 0);
 322 }
 323
 324 int board_early_init_f(void)
 325 {
 326         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 327 #ifdef CONFIG_HAS_FSL_XHCI_USB
 328         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 329         u32 usb_pwrfault;
 330 #endif
 331 #ifdef CONFIG_LPUART
 332         u8 uart;
 333 #endif
 334
 335         /*
 336          * Enable secure system counter for timer
 337          */
 338         out_le32(cntcr, 0x1);
 339
 340 #ifdef CONFIG_SYS_I2C
 341 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 342         i2c_early_init_f();
 343 #endif
 344 #endif
 345         fsl_lsch2_early_init_f();
 346
 347 #ifdef CONFIG_HAS_FSL_XHCI_USB
 348         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 349         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 350         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 351                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 352                         (SCFG_USBPWRFAULT_DEDICATED <<
 353                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 354                         (SCFG_USBPWRFAULT_SHARED <<
 355                         SCFG_USBPWRFAULT_USB1_SHIFT);
 356         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 357 #endif
 358
 359 #ifdef CONFIG_LPUART
 360         /* We use lpuart0 as system console */
 361         uart = QIXIS_READ(brdcfg[14]);
 362         uart &= ~CFG_UART_MUX_MASK;
 363         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 364         QIXIS_WRITE(brdcfg[14], uart);
 365 #endif
 366
 367         return 0;
 368 }
 369
 370 #ifdef CONFIG_FSL_DEEP_SLEEP
 371 /* determine if it is a warm boot */
 372 bool is_warm_boot(void)
 373 {
 374 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 375         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 376
 377         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 378                 return 1;
 379
 380         return 0;
 381 }
 382 #endif
 383
 384 int config_board_mux(int ctrl_type)
 385 {
 386         u8 reg14;
 387
 388         reg14 = QIXIS_READ(brdcfg[14]);
 389
 390         switch (ctrl_type) {
 391         case MUX_TYPE_GPIO:
 392                 reg14 = (reg14 & (~0x6)) | 0x2;
 393                 break;
 394         default:
 395                 puts("Unsupported mux interface type\n");
 396                 return -1;
 397         }
 398
 399         QIXIS_WRITE(brdcfg[14], reg14);
 400
 401         return 0;
 402 }
 403
 404 int config_serdes_mux(void)
 405 {
 406         return 0;
 407 }
 408
 409 #ifdef CONFIG_MISC_INIT_R
 410 int misc_init_r(void)
 411 {
 412         if (hwconfig("gpio"))
 413                 config_board_mux(MUX_TYPE_GPIO);
 414
 415         return 0;
 416 }
 417 #endif
 418
 419 int board_init(void)
 420 {
 421         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 422
 423 #ifdef CONFIG_SYS_FSL_SERDES
 424         config_serdes_mux();
 425 #endif
 426
 427         if (adjust_vdd(0))
 428                 printf("Warning: Adjusting core voltage failed.\n");
 429
 430 #ifdef CONFIG_FSL_LS_PPA
 431         ppa_init();
 432 #endif
 433
 434 #ifdef CONFIG_NXP_ESBC
 435         /*
 436          * In case of Secure Boot, the IBR configures the SMMU
 437          * to allow only Secure transactions.
 438          * SMMU must be reset in bypass mode.
 439          * Set the ClientPD bit and Clear the USFCFG Bit
 440          */
 441         u32 val;
 442         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 443         out_le32(SMMU_SCR0, val);
 444         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 445         out_le32(SMMU_NSCR0, val);
 446 #endif
 447
 448 #ifdef CONFIG_FSL_CAAM
 449         sec_init();
 450 #endif
 451
 452         return 0;
 453 }
 454
 455 #ifdef CONFIG_OF_BOARD_SETUP
 456 int ft_board_setup(void *blob, struct bd_info *bd)
 457 {
 458         u64 base[CONFIG_NR_DRAM_BANKS];
 459         u64 size[CONFIG_NR_DRAM_BANKS];
 460         u8 reg;
 461
 462         /* fixup DT for the two DDR banks */
 463         base[0] = gd->bd->bi_dram[0].start;
 464         size[0] = gd->bd->bi_dram[0].size;
 465         base[1] = gd->bd->bi_dram[1].start;
 466         size[1] = gd->bd->bi_dram[1].size;
 467
 468         fdt_fixup_memory_banks(blob, base, size, 2);
 469         ft_cpu_setup(blob, bd);
 470
 471 #ifdef CONFIG_SYS_DPAA_FMAN
 472 #ifndef CONFIG_DM_ETH
 473         fdt_fixup_fman_ethernet(blob);
 474 #endif
 475         fdt_fixup_board_enet(blob);
 476 #endif
 477
 478         fdt_fixup_icid(blob);
 479
 480         reg = QIXIS_READ(brdcfg[0]);
 481         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 482
 483         /* Disable IFC if QSPI is enabled */
 484         if (reg == 0xF)
 485                 do_fixup_by_compat(blob, "fsl,ifc",
 486                                    "status", "disabled", 8 + 1, 1);
 487
 488         return 0;
 489 }
 490 #endif
 491
 492 u8 flash_read8(void *addr)
 493 {
 494         return __raw_readb(addr + 1);
 495 }
 496
 497 void flash_write16(u16 val, void *addr)
 498 {
 499         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 500
 501         __raw_writew(shftval, addr);
 502 }
 503
 504 u16 flash_read16(void *addr)
 505 {
 506         u16 val = __raw_readw(addr);
 507
 508         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 509 }
 510
 511 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 512 void *env_sf_get_env_addr(void)
 513 {
 514         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 515 }
 516 #endif