1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2019-2020 NXP
9 #include <fdt_support.h>
10 #include <fsl_ddr_sdram.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/fsl_serdes.h>
15 #include <asm/arch/ppa.h>
16 #include <asm/arch/fdt.h>
17 #include <asm/arch/mmu.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <asm/arch-fsl-layerscape/fsl_icid.h>
27 #include <fsl_esdhc.h>
32 #include "../common/vid.h"
33 #include "../common/qixis.h"
34 #include "ls1046aqds_qixis.h"
36 DECLARE_GLOBAL_DATA_PTR;
38 #ifdef CONFIG_SYS_I2C_EARLY_INIT
39 void i2c_early_init_f(void);
43 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
47 CONFIG_SYS_NOR0_CSPR_EXT,
61 CONFIG_SYS_NOR1_CSPR_EXT,
74 CONFIG_SYS_NAND_CSPR_EXT,
75 CONFIG_SYS_NAND_AMASK,
78 CONFIG_SYS_NAND_FTIM0,
79 CONFIG_SYS_NAND_FTIM1,
80 CONFIG_SYS_NAND_FTIM2,
87 CONFIG_SYS_FPGA_CSPR_EXT,
88 CONFIG_SYS_FPGA_AMASK,
91 CONFIG_SYS_FPGA_FTIM0,
92 CONFIG_SYS_FPGA_FTIM1,
93 CONFIG_SYS_FPGA_FTIM2,
99 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
102 CONFIG_SYS_NAND_CSPR,
103 CONFIG_SYS_NAND_CSPR_EXT,
104 CONFIG_SYS_NAND_AMASK,
105 CONFIG_SYS_NAND_CSOR,
107 CONFIG_SYS_NAND_FTIM0,
108 CONFIG_SYS_NAND_FTIM1,
109 CONFIG_SYS_NAND_FTIM2,
110 CONFIG_SYS_NAND_FTIM3
115 CONFIG_SYS_NOR0_CSPR,
116 CONFIG_SYS_NOR0_CSPR_EXT,
117 CONFIG_SYS_NOR_AMASK,
120 CONFIG_SYS_NOR_FTIM0,
121 CONFIG_SYS_NOR_FTIM1,
122 CONFIG_SYS_NOR_FTIM2,
128 CONFIG_SYS_NOR1_CSPR,
129 CONFIG_SYS_NOR1_CSPR_EXT,
130 CONFIG_SYS_NOR_AMASK,
133 CONFIG_SYS_NOR_FTIM0,
134 CONFIG_SYS_NOR_FTIM1,
135 CONFIG_SYS_NOR_FTIM2,
141 CONFIG_SYS_FPGA_CSPR,
142 CONFIG_SYS_FPGA_CSPR_EXT,
143 CONFIG_SYS_FPGA_AMASK,
144 CONFIG_SYS_FPGA_CSOR,
146 CONFIG_SYS_FPGA_FTIM0,
147 CONFIG_SYS_FPGA_FTIM1,
148 CONFIG_SYS_FPGA_FTIM2,
149 CONFIG_SYS_FPGA_FTIM3
154 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
156 enum boot_src src = get_boot_src();
158 if (src == BOOT_SOURCE_IFC_NAND)
159 regs_info->regs = ifc_cfg_nand_boot;
161 regs_info->regs = ifc_cfg_nor_boot;
162 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
173 #ifdef CONFIG_TFABOOT
174 enum boot_src src = get_boot_src();
177 #ifndef CONFIG_SD_BOOT
181 puts("Board: LS1046AQDS, boot from ");
183 #ifdef CONFIG_TFABOOT
184 if (src == BOOT_SOURCE_SD_MMC)
189 #ifdef CONFIG_SD_BOOT
192 sw = QIXIS_READ(brdcfg[0]);
193 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
196 printf("vBank: %d\n", sw);
204 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
207 #ifdef CONFIG_TFABOOT
210 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
211 QIXIS_READ(id), QIXIS_READ(arch));
213 printf("FPGA: v%d (%s), build %d\n",
214 (int)QIXIS_READ(scver), qixis_read_tag(buf),
215 (int)qixis_read_minor());
220 bool if_board_diff_clk(void)
222 u8 diff_conf = QIXIS_READ(brdcfg[11]);
224 return diff_conf & 0x40;
227 unsigned long get_board_sys_clk(void)
229 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
231 switch (sysclk_conf & 0x0f) {
232 case QIXIS_SYSCLK_64:
234 case QIXIS_SYSCLK_83:
236 case QIXIS_SYSCLK_100:
238 case QIXIS_SYSCLK_125:
240 case QIXIS_SYSCLK_133:
242 case QIXIS_SYSCLK_150:
244 case QIXIS_SYSCLK_160:
246 case QIXIS_SYSCLK_166:
253 unsigned long get_board_ddr_clk(void)
255 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
257 if (if_board_diff_clk())
258 return get_board_sys_clk();
259 switch ((ddrclk_conf & 0x30) >> 4) {
260 case QIXIS_DDRCLK_100:
262 case QIXIS_DDRCLK_125:
264 case QIXIS_DDRCLK_133:
272 u32 get_lpuart_clk(void)
278 int select_i2c_ch_pca9547(u8 ch, int bus_num)
284 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
287 printf("%s: Cannot find udev for a bus %d\n", __func__,
291 ret = dm_i2c_write(dev, 0, &ch, 1);
293 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
296 puts("PCA: failed to select proper channel\n");
306 * When resuming from deep sleep, the I2C channel may not be
307 * in the default channel. So, switch to the default channel
308 * before accessing DDR SPD.
310 * PCA9547 mount on I2C1 bus
312 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
314 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
315 defined(CONFIG_SPL_BUILD)
316 /* This will break-before-make MMU for DDR */
317 update_early_mmu_table();
323 int i2c_multiplexer_select_vid_channel(u8 channel)
325 return select_i2c_ch_pca9547(channel, 0);
328 int board_early_init_f(void)
330 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
331 #ifdef CONFIG_HAS_FSL_XHCI_USB
332 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
340 * Enable secure system counter for timer
342 out_le32(cntcr, 0x1);
344 #ifdef CONFIG_SYS_I2C_EARLY_INIT
347 fsl_lsch2_early_init_f();
349 #ifdef CONFIG_HAS_FSL_XHCI_USB
350 out_be32(&scfg->rcwpmuxcr0, 0x3333);
351 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
352 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
353 SCFG_USBPWRFAULT_USB3_SHIFT) |
354 (SCFG_USBPWRFAULT_DEDICATED <<
355 SCFG_USBPWRFAULT_USB2_SHIFT) |
356 (SCFG_USBPWRFAULT_SHARED <<
357 SCFG_USBPWRFAULT_USB1_SHIFT);
358 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
362 /* We use lpuart0 as system console */
363 uart = QIXIS_READ(brdcfg[14]);
364 uart &= ~CFG_UART_MUX_MASK;
365 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
366 QIXIS_WRITE(brdcfg[14], uart);
372 #ifdef CONFIG_FSL_DEEP_SLEEP
373 /* determine if it is a warm boot */
374 bool is_warm_boot(void)
376 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
377 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
379 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
386 int config_board_mux(int ctrl_type)
390 reg14 = QIXIS_READ(brdcfg[14]);
394 reg14 = (reg14 & (~0x6)) | 0x2;
397 puts("Unsupported mux interface type\n");
401 QIXIS_WRITE(brdcfg[14], reg14);
406 int config_serdes_mux(void)
411 #ifdef CONFIG_MISC_INIT_R
412 int misc_init_r(void)
414 if (hwconfig("gpio"))
415 config_board_mux(MUX_TYPE_GPIO);
423 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
425 #ifdef CONFIG_SYS_FSL_SERDES
430 printf("Warning: Adjusting core voltage failed.\n");
432 #ifdef CONFIG_FSL_LS_PPA
436 #ifdef CONFIG_NXP_ESBC
438 * In case of Secure Boot, the IBR configures the SMMU
439 * to allow only Secure transactions.
440 * SMMU must be reset in bypass mode.
441 * Set the ClientPD bit and Clear the USFCFG Bit
444 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
445 out_le32(SMMU_SCR0, val);
446 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
447 out_le32(SMMU_NSCR0, val);
450 #ifdef CONFIG_FSL_CAAM
457 #ifdef CONFIG_OF_BOARD_SETUP
458 int ft_board_setup(void *blob, struct bd_info *bd)
460 u64 base[CONFIG_NR_DRAM_BANKS];
461 u64 size[CONFIG_NR_DRAM_BANKS];
464 /* fixup DT for the two DDR banks */
465 base[0] = gd->bd->bi_dram[0].start;
466 size[0] = gd->bd->bi_dram[0].size;
467 base[1] = gd->bd->bi_dram[1].start;
468 size[1] = gd->bd->bi_dram[1].size;
470 fdt_fixup_memory_banks(blob, base, size, 2);
471 ft_cpu_setup(blob, bd);
473 #ifdef CONFIG_SYS_DPAA_FMAN
474 #ifndef CONFIG_DM_ETH
475 fdt_fixup_fman_ethernet(blob);
477 fdt_fixup_board_enet(blob);
480 fdt_fixup_icid(blob);
482 reg = QIXIS_READ(brdcfg[0]);
483 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
485 /* Disable IFC if QSPI is enabled */
487 do_fixup_by_compat(blob, "fsl,ifc",
488 "status", "disabled", 8 + 1, 1);
494 u8 flash_read8(void *addr)
496 return __raw_readb(addr + 1);
499 void flash_write16(u16 val, void *addr)
501 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
503 __raw_writew(shftval, addr);
506 u16 flash_read16(void *addr)
508 u16 val = __raw_readw(addr);
510 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
513 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
514 void *env_sf_get_env_addr(void)
516 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);