board/freescale/ls1046aqds/ls1046aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <i2c.h>
  10 #include <fdt_support.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <init.h>
  13 #include <asm/global_data.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/fsl_serdes.h>
  17 #include <asm/arch/ppa.h>
  18 #include <asm/arch/fdt.h>
  19 #include <asm/arch/mmu.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/soc.h>
  22 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  23 #include <ahci.h>
  24 #include <hwconfig.h>
  25 #include <mmc.h>
  26 #include <scsi.h>
  27 #include <fm_eth.h>
  28 #include <fsl_csu.h>
  29 #include <fsl_esdhc.h>
  30 #include <fsl_ifc.h>
  31 #include <fsl_sec.h>
  32 #include <spl.h>
  33 #include "../common/i2c_mux.h"
  34
  35 #include "../common/vid.h"
  36 #include "../common/qixis.h"
  37 #include "ls1046aqds_qixis.h"
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #ifdef CONFIG_TFABOOT
  42 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  43         {
  44                 "nor0",
  45                 CONFIG_SYS_NOR0_CSPR,
  46                 CONFIG_SYS_NOR0_CSPR_EXT,
  47                 CONFIG_SYS_NOR_AMASK,
  48                 CONFIG_SYS_NOR_CSOR,
  49                 {
  50                         CONFIG_SYS_NOR_FTIM0,
  51                         CONFIG_SYS_NOR_FTIM1,
  52                         CONFIG_SYS_NOR_FTIM2,
  53                         CONFIG_SYS_NOR_FTIM3
  54                 },
  55
  56         },
  57         {
  58                 "nor1",
  59                 CONFIG_SYS_NOR1_CSPR,
  60                 CONFIG_SYS_NOR1_CSPR_EXT,
  61                 CONFIG_SYS_NOR_AMASK,
  62                 CONFIG_SYS_NOR_CSOR,
  63                 {
  64                         CONFIG_SYS_NOR_FTIM0,
  65                         CONFIG_SYS_NOR_FTIM1,
  66                         CONFIG_SYS_NOR_FTIM2,
  67                         CONFIG_SYS_NOR_FTIM3
  68                 },
  69         },
  70         {
  71                 "nand",
  72                 CONFIG_SYS_NAND_CSPR,
  73                 CONFIG_SYS_NAND_CSPR_EXT,
  74                 CONFIG_SYS_NAND_AMASK,
  75                 CONFIG_SYS_NAND_CSOR,
  76                 {
  77                         CONFIG_SYS_NAND_FTIM0,
  78                         CONFIG_SYS_NAND_FTIM1,
  79                         CONFIG_SYS_NAND_FTIM2,
  80                         CONFIG_SYS_NAND_FTIM3
  81                 },
  82         },
  83         {
  84                 "fpga",
  85                 CONFIG_SYS_FPGA_CSPR,
  86                 CONFIG_SYS_FPGA_CSPR_EXT,
  87                 CONFIG_SYS_FPGA_AMASK,
  88                 CONFIG_SYS_FPGA_CSOR,
  89                 {
  90                         CONFIG_SYS_FPGA_FTIM0,
  91                         CONFIG_SYS_FPGA_FTIM1,
  92                         CONFIG_SYS_FPGA_FTIM2,
  93                         CONFIG_SYS_FPGA_FTIM3
  94                 },
  95         }
  96 };
  97
  98 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  99         {
 100                 "nand",
 101                 CONFIG_SYS_NAND_CSPR,
 102                 CONFIG_SYS_NAND_CSPR_EXT,
 103                 CONFIG_SYS_NAND_AMASK,
 104                 CONFIG_SYS_NAND_CSOR,
 105                 {
 106                         CONFIG_SYS_NAND_FTIM0,
 107                         CONFIG_SYS_NAND_FTIM1,
 108                         CONFIG_SYS_NAND_FTIM2,
 109                         CONFIG_SYS_NAND_FTIM3
 110                 },
 111         },
 112         {
 113                 "nor0",
 114                 CONFIG_SYS_NOR0_CSPR,
 115                 CONFIG_SYS_NOR0_CSPR_EXT,
 116                 CONFIG_SYS_NOR_AMASK,
 117                 CONFIG_SYS_NOR_CSOR,
 118                 {
 119                         CONFIG_SYS_NOR_FTIM0,
 120                         CONFIG_SYS_NOR_FTIM1,
 121                         CONFIG_SYS_NOR_FTIM2,
 122                         CONFIG_SYS_NOR_FTIM3
 123                 },
 124         },
 125         {
 126                 "nor1",
 127                 CONFIG_SYS_NOR1_CSPR,
 128                 CONFIG_SYS_NOR1_CSPR_EXT,
 129                 CONFIG_SYS_NOR_AMASK,
 130                 CONFIG_SYS_NOR_CSOR,
 131                 {
 132                         CONFIG_SYS_NOR_FTIM0,
 133                         CONFIG_SYS_NOR_FTIM1,
 134                         CONFIG_SYS_NOR_FTIM2,
 135                         CONFIG_SYS_NOR_FTIM3
 136                 },
 137         },
 138         {
 139                 "fpga",
 140                 CONFIG_SYS_FPGA_CSPR,
 141                 CONFIG_SYS_FPGA_CSPR_EXT,
 142                 CONFIG_SYS_FPGA_AMASK,
 143                 CONFIG_SYS_FPGA_CSOR,
 144                 {
 145                         CONFIG_SYS_FPGA_FTIM0,
 146                         CONFIG_SYS_FPGA_FTIM1,
 147                         CONFIG_SYS_FPGA_FTIM2,
 148                         CONFIG_SYS_FPGA_FTIM3
 149                 },
 150         }
 151 };
 152
 153 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 154 {
 155         enum boot_src src = get_boot_src();
 156
 157         if (src == BOOT_SOURCE_IFC_NAND)
 158                 regs_info->regs = ifc_cfg_nand_boot;
 159         else
 160                 regs_info->regs = ifc_cfg_nor_boot;
 161         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 162 }
 163
 164 #endif
 165
 166 enum {
 167         MUX_TYPE_GPIO,
 168 };
 169
 170 int checkboard(void)
 171 {
 172 #ifdef CONFIG_TFABOOT
 173         enum boot_src src = get_boot_src();
 174 #endif
 175         char buf[64];
 176 #ifndef CONFIG_SD_BOOT
 177         u8 sw;
 178 #endif
 179
 180         puts("Board: LS1046AQDS, boot from ");
 181
 182 #ifdef CONFIG_TFABOOT
 183         if (src == BOOT_SOURCE_SD_MMC)
 184                 puts("SD\n");
 185         else {
 186 #endif
 187
 188 #ifdef CONFIG_SD_BOOT
 189         puts("SD\n");
 190 #else
 191         sw = QIXIS_READ(brdcfg[0]);
 192         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 193
 194         if (sw < 0x8)
 195                 printf("vBank: %d\n", sw);
 196         else if (sw == 0x8)
 197                 puts("PromJet\n");
 198         else if (sw == 0x9)
 199                 puts("NAND\n");
 200         else if (sw == 0xF)
 201                 printf("QSPI\n");
 202         else
 203                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 204 #endif
 205
 206 #ifdef CONFIG_TFABOOT
 207         }
 208 #endif
 209         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 210                QIXIS_READ(id), QIXIS_READ(arch));
 211
 212         printf("FPGA:  v%d (%s), build %d\n",
 213                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 214                (int)qixis_read_minor());
 215
 216         return 0;
 217 }
 218
 219 bool if_board_diff_clk(void)
 220 {
 221         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 222
 223         return diff_conf & 0x40;
 224 }
 225
 226 unsigned long get_board_sys_clk(void)
 227 {
 228         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 229
 230         switch (sysclk_conf & 0x0f) {
 231         case QIXIS_SYSCLK_64:
 232                 return 64000000;
 233         case QIXIS_SYSCLK_83:
 234                 return 83333333;
 235         case QIXIS_SYSCLK_100:
 236                 return 100000000;
 237         case QIXIS_SYSCLK_125:
 238                 return 125000000;
 239         case QIXIS_SYSCLK_133:
 240                 return 133333333;
 241         case QIXIS_SYSCLK_150:
 242                 return 150000000;
 243         case QIXIS_SYSCLK_160:
 244                 return 160000000;
 245         case QIXIS_SYSCLK_166:
 246                 return 166666666;
 247         }
 248
 249         return 66666666;
 250 }
 251
 252 unsigned long get_board_ddr_clk(void)
 253 {
 254         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 255
 256         if (if_board_diff_clk())
 257                 return get_board_sys_clk();
 258         switch ((ddrclk_conf & 0x30) >> 4) {
 259         case QIXIS_DDRCLK_100:
 260                 return 100000000;
 261         case QIXIS_DDRCLK_125:
 262                 return 125000000;
 263         case QIXIS_DDRCLK_133:
 264                 return 133333333;
 265         }
 266
 267         return 66666666;
 268 }
 269
 270 #ifdef CONFIG_LPUART
 271 u32 get_lpuart_clk(void)
 272 {
 273         return gd->bus_clk;
 274 }
 275 #endif
 276
 277 int dram_init(void)
 278 {
 279         /*
 280          * When resuming from deep sleep, the I2C channel may not be
 281          * in the default channel. So, switch to the default channel
 282          * before accessing DDR SPD.
 283          *
 284          * PCA9547 mount on I2C1 bus
 285          */
 286         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 287         fsl_initdram();
 288 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 289         defined(CONFIG_SPL_BUILD)
 290         /* This will break-before-make MMU for DDR */
 291         update_early_mmu_table();
 292 #endif
 293
 294         return 0;
 295 }
 296
 297 int i2c_multiplexer_select_vid_channel(u8 channel)
 298 {
 299         return select_i2c_ch_pca9547(channel, 0);
 300 }
 301
 302 int board_early_init_f(void)
 303 {
 304         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 305 #ifdef CONFIG_HAS_FSL_XHCI_USB
 306         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 307         u32 usb_pwrfault;
 308 #endif
 309 #ifdef CONFIG_LPUART
 310         u8 uart;
 311 #endif
 312
 313         /*
 314          * Enable secure system counter for timer
 315          */
 316         out_le32(cntcr, 0x1);
 317
 318 #if defined(CONFIG_SYS_I2C_EARLY_INIT)
 319         i2c_early_init_f();
 320 #endif
 321         fsl_lsch2_early_init_f();
 322
 323 #ifdef CONFIG_HAS_FSL_XHCI_USB
 324         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 325         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 326         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 327                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 328                         (SCFG_USBPWRFAULT_DEDICATED <<
 329                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 330                         (SCFG_USBPWRFAULT_SHARED <<
 331                         SCFG_USBPWRFAULT_USB1_SHIFT);
 332         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 333 #endif
 334
 335 #ifdef CONFIG_LPUART
 336         /* We use lpuart0 as system console */
 337         uart = QIXIS_READ(brdcfg[14]);
 338         uart &= ~CFG_UART_MUX_MASK;
 339         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 340         QIXIS_WRITE(brdcfg[14], uart);
 341 #endif
 342
 343         return 0;
 344 }
 345
 346 #ifdef CONFIG_FSL_DEEP_SLEEP
 347 /* determine if it is a warm boot */
 348 bool is_warm_boot(void)
 349 {
 350 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 351         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 352
 353         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 354                 return 1;
 355
 356         return 0;
 357 }
 358 #endif
 359
 360 int config_board_mux(int ctrl_type)
 361 {
 362         u8 reg14;
 363
 364         reg14 = QIXIS_READ(brdcfg[14]);
 365
 366         switch (ctrl_type) {
 367         case MUX_TYPE_GPIO:
 368                 reg14 = (reg14 & (~0x6)) | 0x2;
 369                 break;
 370         default:
 371                 puts("Unsupported mux interface type\n");
 372                 return -1;
 373         }
 374
 375         QIXIS_WRITE(brdcfg[14], reg14);
 376
 377         return 0;
 378 }
 379
 380 int config_serdes_mux(void)
 381 {
 382         return 0;
 383 }
 384
 385 #ifdef CONFIG_MISC_INIT_R
 386 int misc_init_r(void)
 387 {
 388         if (hwconfig("gpio"))
 389                 config_board_mux(MUX_TYPE_GPIO);
 390
 391         return 0;
 392 }
 393 #endif
 394
 395 int board_init(void)
 396 {
 397         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 398
 399 #ifdef CONFIG_SYS_FSL_SERDES
 400         config_serdes_mux();
 401 #endif
 402
 403         if (adjust_vdd(0))
 404                 printf("Warning: Adjusting core voltage failed.\n");
 405
 406 #ifdef CONFIG_FSL_LS_PPA
 407         ppa_init();
 408 #endif
 409
 410 #ifdef CONFIG_NXP_ESBC
 411         /*
 412          * In case of Secure Boot, the IBR configures the SMMU
 413          * to allow only Secure transactions.
 414          * SMMU must be reset in bypass mode.
 415          * Set the ClientPD bit and Clear the USFCFG Bit
 416          */
 417         u32 val;
 418         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 419         out_le32(SMMU_SCR0, val);
 420         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 421         out_le32(SMMU_NSCR0, val);
 422 #endif
 423
 424 #ifdef CONFIG_FSL_CAAM
 425         sec_init();
 426 #endif
 427
 428         return 0;
 429 }
 430
 431 #ifdef CONFIG_OF_BOARD_SETUP
 432 int ft_board_setup(void *blob, struct bd_info *bd)
 433 {
 434         u64 base[CONFIG_NR_DRAM_BANKS];
 435         u64 size[CONFIG_NR_DRAM_BANKS];
 436         u8 reg;
 437
 438         /* fixup DT for the two DDR banks */
 439         base[0] = gd->bd->bi_dram[0].start;
 440         size[0] = gd->bd->bi_dram[0].size;
 441         base[1] = gd->bd->bi_dram[1].start;
 442         size[1] = gd->bd->bi_dram[1].size;
 443
 444         fdt_fixup_memory_banks(blob, base, size, 2);
 445         ft_cpu_setup(blob, bd);
 446
 447 #ifdef CONFIG_SYS_DPAA_FMAN
 448 #ifndef CONFIG_DM_ETH
 449         fdt_fixup_fman_ethernet(blob);
 450 #endif
 451         fdt_fixup_board_enet(blob);
 452 #endif
 453
 454         fdt_fixup_icid(blob);
 455
 456         reg = QIXIS_READ(brdcfg[0]);
 457         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 458
 459         /* Disable IFC if QSPI is enabled */
 460         if (reg == 0xF)
 461                 do_fixup_by_compat(blob, "fsl,ifc",
 462                                    "status", "disabled", 8 + 1, 1);
 463
 464         return 0;
 465 }
 466 #endif
 467
 468 u8 flash_read8(void *addr)
 469 {
 470         return __raw_readb(addr + 1);
 471 }
 472
 473 void flash_write16(u16 val, void *addr)
 474 {
 475         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 476
 477         __raw_writew(shftval, addr);
 478 }
 479
 480 u16 flash_read16(void *addr)
 481 {
 482         u16 val = __raw_readw(addr);
 483
 484         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 485 }
 486
 487 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 488 void *env_sf_get_env_addr(void)
 489 {
 490         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 491 }
 492 #endif