board/freescale/ls1046aqds/ls1046aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ppa.h>
  15 #include <asm/arch/fdt.h>
  16 #include <asm/arch/mmu.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/soc.h>
  19 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  20 #include <ahci.h>
  21 #include <hwconfig.h>
  22 #include <mmc.h>
  23 #include <scsi.h>
  24 #include <fm_eth.h>
  25 #include <fsl_csu.h>
  26 #include <fsl_esdhc.h>
  27 #include <fsl_ifc.h>
  28 #include <fsl_sec.h>
  29 #include <spl.h>
  30
  31 #include "../common/vid.h"
  32 #include "../common/qixis.h"
  33 #include "ls1046aqds_qixis.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_TFABOOT
  38 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  39         {
  40                 "nor0",
  41                 CONFIG_SYS_NOR0_CSPR,
  42                 CONFIG_SYS_NOR0_CSPR_EXT,
  43                 CONFIG_SYS_NOR_AMASK,
  44                 CONFIG_SYS_NOR_CSOR,
  45                 {
  46                         CONFIG_SYS_NOR_FTIM0,
  47                         CONFIG_SYS_NOR_FTIM1,
  48                         CONFIG_SYS_NOR_FTIM2,
  49                         CONFIG_SYS_NOR_FTIM3
  50                 },
  51
  52         },
  53         {
  54                 "nor1",
  55                 CONFIG_SYS_NOR1_CSPR,
  56                 CONFIG_SYS_NOR1_CSPR_EXT,
  57                 CONFIG_SYS_NOR_AMASK,
  58                 CONFIG_SYS_NOR_CSOR,
  59                 {
  60                         CONFIG_SYS_NOR_FTIM0,
  61                         CONFIG_SYS_NOR_FTIM1,
  62                         CONFIG_SYS_NOR_FTIM2,
  63                         CONFIG_SYS_NOR_FTIM3
  64                 },
  65         },
  66         {
  67                 "nand",
  68                 CONFIG_SYS_NAND_CSPR,
  69                 CONFIG_SYS_NAND_CSPR_EXT,
  70                 CONFIG_SYS_NAND_AMASK,
  71                 CONFIG_SYS_NAND_CSOR,
  72                 {
  73                         CONFIG_SYS_NAND_FTIM0,
  74                         CONFIG_SYS_NAND_FTIM1,
  75                         CONFIG_SYS_NAND_FTIM2,
  76                         CONFIG_SYS_NAND_FTIM3
  77                 },
  78         },
  79         {
  80                 "fpga",
  81                 CONFIG_SYS_FPGA_CSPR,
  82                 CONFIG_SYS_FPGA_CSPR_EXT,
  83                 CONFIG_SYS_FPGA_AMASK,
  84                 CONFIG_SYS_FPGA_CSOR,
  85                 {
  86                         CONFIG_SYS_FPGA_FTIM0,
  87                         CONFIG_SYS_FPGA_FTIM1,
  88                         CONFIG_SYS_FPGA_FTIM2,
  89                         CONFIG_SYS_FPGA_FTIM3
  90                 },
  91         }
  92 };
  93
  94 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  95         {
  96                 "nand",
  97                 CONFIG_SYS_NAND_CSPR,
  98                 CONFIG_SYS_NAND_CSPR_EXT,
  99                 CONFIG_SYS_NAND_AMASK,
 100                 CONFIG_SYS_NAND_CSOR,
 101                 {
 102                         CONFIG_SYS_NAND_FTIM0,
 103                         CONFIG_SYS_NAND_FTIM1,
 104                         CONFIG_SYS_NAND_FTIM2,
 105                         CONFIG_SYS_NAND_FTIM3
 106                 },
 107         },
 108         {
 109                 "nor0",
 110                 CONFIG_SYS_NOR0_CSPR,
 111                 CONFIG_SYS_NOR0_CSPR_EXT,
 112                 CONFIG_SYS_NOR_AMASK,
 113                 CONFIG_SYS_NOR_CSOR,
 114                 {
 115                         CONFIG_SYS_NOR_FTIM0,
 116                         CONFIG_SYS_NOR_FTIM1,
 117                         CONFIG_SYS_NOR_FTIM2,
 118                         CONFIG_SYS_NOR_FTIM3
 119                 },
 120         },
 121         {
 122                 "nor1",
 123                 CONFIG_SYS_NOR1_CSPR,
 124                 CONFIG_SYS_NOR1_CSPR_EXT,
 125                 CONFIG_SYS_NOR_AMASK,
 126                 CONFIG_SYS_NOR_CSOR,
 127                 {
 128                         CONFIG_SYS_NOR_FTIM0,
 129                         CONFIG_SYS_NOR_FTIM1,
 130                         CONFIG_SYS_NOR_FTIM2,
 131                         CONFIG_SYS_NOR_FTIM3
 132                 },
 133         },
 134         {
 135                 "fpga",
 136                 CONFIG_SYS_FPGA_CSPR,
 137                 CONFIG_SYS_FPGA_CSPR_EXT,
 138                 CONFIG_SYS_FPGA_AMASK,
 139                 CONFIG_SYS_FPGA_CSOR,
 140                 {
 141                         CONFIG_SYS_FPGA_FTIM0,
 142                         CONFIG_SYS_FPGA_FTIM1,
 143                         CONFIG_SYS_FPGA_FTIM2,
 144                         CONFIG_SYS_FPGA_FTIM3
 145                 },
 146         }
 147 };
 148
 149 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 150 {
 151         enum boot_src src = get_boot_src();
 152
 153         if (src == BOOT_SOURCE_IFC_NAND)
 154                 regs_info->regs = ifc_cfg_nand_boot;
 155         else
 156                 regs_info->regs = ifc_cfg_nor_boot;
 157         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 158 }
 159
 160 #endif
 161
 162 enum {
 163         MUX_TYPE_GPIO,
 164 };
 165
 166 int checkboard(void)
 167 {
 168 #ifdef CONFIG_TFABOOT
 169         enum boot_src src = get_boot_src();
 170 #endif
 171         char buf[64];
 172 #ifndef CONFIG_SD_BOOT
 173         u8 sw;
 174 #endif
 175
 176         puts("Board: LS1046AQDS, boot from ");
 177
 178 #ifdef CONFIG_TFABOOT
 179         if (src == BOOT_SOURCE_SD_MMC)
 180                 puts("SD\n");
 181         else {
 182 #endif
 183
 184 #ifdef CONFIG_SD_BOOT
 185         puts("SD\n");
 186 #else
 187         sw = QIXIS_READ(brdcfg[0]);
 188         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 189
 190         if (sw < 0x8)
 191                 printf("vBank: %d\n", sw);
 192         else if (sw == 0x8)
 193                 puts("PromJet\n");
 194         else if (sw == 0x9)
 195                 puts("NAND\n");
 196         else if (sw == 0xF)
 197                 printf("QSPI\n");
 198         else
 199                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 200 #endif
 201
 202 #ifdef CONFIG_TFABOOT
 203         }
 204 #endif
 205         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 206                QIXIS_READ(id), QIXIS_READ(arch));
 207
 208         printf("FPGA:  v%d (%s), build %d\n",
 209                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 210                (int)qixis_read_minor());
 211
 212         return 0;
 213 }
 214
 215 bool if_board_diff_clk(void)
 216 {
 217         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 218
 219         return diff_conf & 0x40;
 220 }
 221
 222 unsigned long get_board_sys_clk(void)
 223 {
 224         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 225
 226         switch (sysclk_conf & 0x0f) {
 227         case QIXIS_SYSCLK_64:
 228                 return 64000000;
 229         case QIXIS_SYSCLK_83:
 230                 return 83333333;
 231         case QIXIS_SYSCLK_100:
 232                 return 100000000;
 233         case QIXIS_SYSCLK_125:
 234                 return 125000000;
 235         case QIXIS_SYSCLK_133:
 236                 return 133333333;
 237         case QIXIS_SYSCLK_150:
 238                 return 150000000;
 239         case QIXIS_SYSCLK_160:
 240                 return 160000000;
 241         case QIXIS_SYSCLK_166:
 242                 return 166666666;
 243         }
 244
 245         return 66666666;
 246 }
 247
 248 unsigned long get_board_ddr_clk(void)
 249 {
 250         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 251
 252         if (if_board_diff_clk())
 253                 return get_board_sys_clk();
 254         switch ((ddrclk_conf & 0x30) >> 4) {
 255         case QIXIS_DDRCLK_100:
 256                 return 100000000;
 257         case QIXIS_DDRCLK_125:
 258                 return 125000000;
 259         case QIXIS_DDRCLK_133:
 260                 return 133333333;
 261         }
 262
 263         return 66666666;
 264 }
 265
 266 #ifdef CONFIG_LPUART
 267 u32 get_lpuart_clk(void)
 268 {
 269         return gd->bus_clk;
 270 }
 271 #endif
 272
 273 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 274 {
 275         int ret;
 276 #ifdef CONFIG_DM_I2C
 277         struct udevice *dev;
 278
 279         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 280                                       1, &dev);
 281         if (ret) {
 282                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 283                        bus_num);
 284                 return ret;
 285         }
 286         ret = dm_i2c_write(dev, 0, &ch, 1);
 287 #else
 288         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 289 #endif
 290         if (ret) {
 291                 puts("PCA: failed to select proper channel\n");
 292                 return ret;
 293         }
 294
 295         return 0;
 296 }
 297
 298 int dram_init(void)
 299 {
 300         /*
 301          * When resuming from deep sleep, the I2C channel may not be
 302          * in the default channel. So, switch to the default channel
 303          * before accessing DDR SPD.
 304          *
 305          * PCA9547 mount on I2C1 bus
 306          */
 307         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 308         fsl_initdram();
 309 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 310         defined(CONFIG_SPL_BUILD)
 311         /* This will break-before-make MMU for DDR */
 312         update_early_mmu_table();
 313 #endif
 314
 315         return 0;
 316 }
 317
 318 int i2c_multiplexer_select_vid_channel(u8 channel)
 319 {
 320         return select_i2c_ch_pca9547(channel, 0);
 321 }
 322
 323 int board_early_init_f(void)
 324 {
 325 #ifdef CONFIG_HAS_FSL_XHCI_USB
 326         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 327         u32 usb_pwrfault;
 328 #endif
 329 #ifdef CONFIG_LPUART
 330         u8 uart;
 331 #endif
 332
 333 #ifdef CONFIG_SYS_I2C
 334 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 335         i2c_early_init_f();
 336 #endif
 337 #endif
 338         fsl_lsch2_early_init_f();
 339
 340 #ifdef CONFIG_HAS_FSL_XHCI_USB
 341         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 342         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 343         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 344                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 345                         (SCFG_USBPWRFAULT_DEDICATED <<
 346                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 347                         (SCFG_USBPWRFAULT_SHARED <<
 348                         SCFG_USBPWRFAULT_USB1_SHIFT);
 349         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 350 #endif
 351
 352 #ifdef CONFIG_LPUART
 353         /* We use lpuart0 as system console */
 354         uart = QIXIS_READ(brdcfg[14]);
 355         uart &= ~CFG_UART_MUX_MASK;
 356         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 357         QIXIS_WRITE(brdcfg[14], uart);
 358 #endif
 359
 360         return 0;
 361 }
 362
 363 #ifdef CONFIG_FSL_DEEP_SLEEP
 364 /* determine if it is a warm boot */
 365 bool is_warm_boot(void)
 366 {
 367 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 368         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 369
 370         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 371                 return 1;
 372
 373         return 0;
 374 }
 375 #endif
 376
 377 int config_board_mux(int ctrl_type)
 378 {
 379         u8 reg14;
 380
 381         reg14 = QIXIS_READ(brdcfg[14]);
 382
 383         switch (ctrl_type) {
 384         case MUX_TYPE_GPIO:
 385                 reg14 = (reg14 & (~0x6)) | 0x2;
 386                 break;
 387         default:
 388                 puts("Unsupported mux interface type\n");
 389                 return -1;
 390         }
 391
 392         QIXIS_WRITE(brdcfg[14], reg14);
 393
 394         return 0;
 395 }
 396
 397 int config_serdes_mux(void)
 398 {
 399         return 0;
 400 }
 401
 402 #ifdef CONFIG_MISC_INIT_R
 403 int misc_init_r(void)
 404 {
 405         if (hwconfig("gpio"))
 406                 config_board_mux(MUX_TYPE_GPIO);
 407
 408         return 0;
 409 }
 410 #endif
 411
 412 int board_init(void)
 413 {
 414         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 415
 416 #ifdef CONFIG_SYS_FSL_SERDES
 417         config_serdes_mux();
 418 #endif
 419
 420         if (adjust_vdd(0))
 421                 printf("Warning: Adjusting core voltage failed.\n");
 422
 423 #ifdef CONFIG_FSL_LS_PPA
 424         ppa_init();
 425 #endif
 426
 427 #ifdef CONFIG_NXP_ESBC
 428         /*
 429          * In case of Secure Boot, the IBR configures the SMMU
 430          * to allow only Secure transactions.
 431          * SMMU must be reset in bypass mode.
 432          * Set the ClientPD bit and Clear the USFCFG Bit
 433          */
 434         u32 val;
 435         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 436         out_le32(SMMU_SCR0, val);
 437         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 438         out_le32(SMMU_NSCR0, val);
 439 #endif
 440
 441 #ifdef CONFIG_FSL_CAAM
 442         sec_init();
 443 #endif
 444
 445         return 0;
 446 }
 447
 448 #ifdef CONFIG_OF_BOARD_SETUP
 449 int ft_board_setup(void *blob, bd_t *bd)
 450 {
 451         u64 base[CONFIG_NR_DRAM_BANKS];
 452         u64 size[CONFIG_NR_DRAM_BANKS];
 453         u8 reg;
 454
 455         /* fixup DT for the two DDR banks */
 456         base[0] = gd->bd->bi_dram[0].start;
 457         size[0] = gd->bd->bi_dram[0].size;
 458         base[1] = gd->bd->bi_dram[1].start;
 459         size[1] = gd->bd->bi_dram[1].size;
 460
 461         fdt_fixup_memory_banks(blob, base, size, 2);
 462         ft_cpu_setup(blob, bd);
 463
 464 #ifdef CONFIG_SYS_DPAA_FMAN
 465         fdt_fixup_fman_ethernet(blob);
 466         fdt_fixup_board_enet(blob);
 467 #endif
 468
 469         fdt_fixup_icid(blob);
 470
 471         reg = QIXIS_READ(brdcfg[0]);
 472         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 473
 474         /* Disable IFC if QSPI is enabled */
 475         if (reg == 0xF)
 476                 do_fixup_by_compat(blob, "fsl,ifc",
 477                                    "status", "disabled", 8 + 1, 1);
 478
 479         return 0;
 480 }
 481 #endif
 482
 483 u8 flash_read8(void *addr)
 484 {
 485         return __raw_readb(addr + 1);
 486 }
 487
 488 void flash_write16(u16 val, void *addr)
 489 {
 490         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 491
 492         __raw_writew(shftval, addr);
 493 }
 494
 495 u16 flash_read16(void *addr)
 496 {
 497         u16 val = __raw_readw(addr);
 498
 499         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 500 }
 501
 502 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 503 void *env_sf_get_env_addr(void)
 504 {
 505         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 506 }
 507 #endif