board/freescale/ls1046aqds/ls1046aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <fdt_support.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/ppa.h>
  14 #include <asm/arch/fdt.h>
  15 #include <asm/arch/mmu.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/soc.h>
  18 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  19 #include <ahci.h>
  20 #include <hwconfig.h>
  21 #include <mmc.h>
  22 #include <scsi.h>
  23 #include <fm_eth.h>
  24 #include <fsl_csu.h>
  25 #include <fsl_esdhc.h>
  26 #include <fsl_ifc.h>
  27 #include <fsl_sec.h>
  28 #include <spl.h>
  29
  30 #include "../common/vid.h"
  31 #include "../common/qixis.h"
  32 #include "ls1046aqds_qixis.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #ifdef CONFIG_TFABOOT
  37 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  38         {
  39                 "nor0",
  40                 CONFIG_SYS_NOR0_CSPR,
  41                 CONFIG_SYS_NOR0_CSPR_EXT,
  42                 CONFIG_SYS_NOR_AMASK,
  43                 CONFIG_SYS_NOR_CSOR,
  44                 {
  45                         CONFIG_SYS_NOR_FTIM0,
  46                         CONFIG_SYS_NOR_FTIM1,
  47                         CONFIG_SYS_NOR_FTIM2,
  48                         CONFIG_SYS_NOR_FTIM3
  49                 },
  50
  51         },
  52         {
  53                 "nor1",
  54                 CONFIG_SYS_NOR1_CSPR,
  55                 CONFIG_SYS_NOR1_CSPR_EXT,
  56                 CONFIG_SYS_NOR_AMASK,
  57                 CONFIG_SYS_NOR_CSOR,
  58                 {
  59                         CONFIG_SYS_NOR_FTIM0,
  60                         CONFIG_SYS_NOR_FTIM1,
  61                         CONFIG_SYS_NOR_FTIM2,
  62                         CONFIG_SYS_NOR_FTIM3
  63                 },
  64         },
  65         {
  66                 "nand",
  67                 CONFIG_SYS_NAND_CSPR,
  68                 CONFIG_SYS_NAND_CSPR_EXT,
  69                 CONFIG_SYS_NAND_AMASK,
  70                 CONFIG_SYS_NAND_CSOR,
  71                 {
  72                         CONFIG_SYS_NAND_FTIM0,
  73                         CONFIG_SYS_NAND_FTIM1,
  74                         CONFIG_SYS_NAND_FTIM2,
  75                         CONFIG_SYS_NAND_FTIM3
  76                 },
  77         },
  78         {
  79                 "fpga",
  80                 CONFIG_SYS_FPGA_CSPR,
  81                 CONFIG_SYS_FPGA_CSPR_EXT,
  82                 CONFIG_SYS_FPGA_AMASK,
  83                 CONFIG_SYS_FPGA_CSOR,
  84                 {
  85                         CONFIG_SYS_FPGA_FTIM0,
  86                         CONFIG_SYS_FPGA_FTIM1,
  87                         CONFIG_SYS_FPGA_FTIM2,
  88                         CONFIG_SYS_FPGA_FTIM3
  89                 },
  90         }
  91 };
  92
  93 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  94         {
  95                 "nand",
  96                 CONFIG_SYS_NAND_CSPR,
  97                 CONFIG_SYS_NAND_CSPR_EXT,
  98                 CONFIG_SYS_NAND_AMASK,
  99                 CONFIG_SYS_NAND_CSOR,
 100                 {
 101                         CONFIG_SYS_NAND_FTIM0,
 102                         CONFIG_SYS_NAND_FTIM1,
 103                         CONFIG_SYS_NAND_FTIM2,
 104                         CONFIG_SYS_NAND_FTIM3
 105                 },
 106         },
 107         {
 108                 "nor0",
 109                 CONFIG_SYS_NOR0_CSPR,
 110                 CONFIG_SYS_NOR0_CSPR_EXT,
 111                 CONFIG_SYS_NOR_AMASK,
 112                 CONFIG_SYS_NOR_CSOR,
 113                 {
 114                         CONFIG_SYS_NOR_FTIM0,
 115                         CONFIG_SYS_NOR_FTIM1,
 116                         CONFIG_SYS_NOR_FTIM2,
 117                         CONFIG_SYS_NOR_FTIM3
 118                 },
 119         },
 120         {
 121                 "nor1",
 122                 CONFIG_SYS_NOR1_CSPR,
 123                 CONFIG_SYS_NOR1_CSPR_EXT,
 124                 CONFIG_SYS_NOR_AMASK,
 125                 CONFIG_SYS_NOR_CSOR,
 126                 {
 127                         CONFIG_SYS_NOR_FTIM0,
 128                         CONFIG_SYS_NOR_FTIM1,
 129                         CONFIG_SYS_NOR_FTIM2,
 130                         CONFIG_SYS_NOR_FTIM3
 131                 },
 132         },
 133         {
 134                 "fpga",
 135                 CONFIG_SYS_FPGA_CSPR,
 136                 CONFIG_SYS_FPGA_CSPR_EXT,
 137                 CONFIG_SYS_FPGA_AMASK,
 138                 CONFIG_SYS_FPGA_CSOR,
 139                 {
 140                         CONFIG_SYS_FPGA_FTIM0,
 141                         CONFIG_SYS_FPGA_FTIM1,
 142                         CONFIG_SYS_FPGA_FTIM2,
 143                         CONFIG_SYS_FPGA_FTIM3
 144                 },
 145         }
 146 };
 147
 148 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 149 {
 150         enum boot_src src = get_boot_src();
 151
 152         if (src == BOOT_SOURCE_IFC_NAND)
 153                 regs_info->regs = ifc_cfg_nand_boot;
 154         else
 155                 regs_info->regs = ifc_cfg_nor_boot;
 156         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 157 }
 158
 159 #endif
 160
 161 enum {
 162         MUX_TYPE_GPIO,
 163 };
 164
 165 int checkboard(void)
 166 {
 167 #ifdef CONFIG_TFABOOT
 168         enum boot_src src = get_boot_src();
 169 #endif
 170         char buf[64];
 171 #ifndef CONFIG_SD_BOOT
 172         u8 sw;
 173 #endif
 174
 175         puts("Board: LS1046AQDS, boot from ");
 176
 177 #ifdef CONFIG_TFABOOT
 178         if (src == BOOT_SOURCE_SD_MMC)
 179                 puts("SD\n");
 180         else {
 181 #endif
 182
 183 #ifdef CONFIG_SD_BOOT
 184         puts("SD\n");
 185 #else
 186         sw = QIXIS_READ(brdcfg[0]);
 187         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 188
 189         if (sw < 0x8)
 190                 printf("vBank: %d\n", sw);
 191         else if (sw == 0x8)
 192                 puts("PromJet\n");
 193         else if (sw == 0x9)
 194                 puts("NAND\n");
 195         else if (sw == 0xF)
 196                 printf("QSPI\n");
 197         else
 198                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 199 #endif
 200
 201 #ifdef CONFIG_TFABOOT
 202         }
 203 #endif
 204         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 205                QIXIS_READ(id), QIXIS_READ(arch));
 206
 207         printf("FPGA:  v%d (%s), build %d\n",
 208                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 209                (int)qixis_read_minor());
 210
 211         return 0;
 212 }
 213
 214 bool if_board_diff_clk(void)
 215 {
 216         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 217
 218         return diff_conf & 0x40;
 219 }
 220
 221 unsigned long get_board_sys_clk(void)
 222 {
 223         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 224
 225         switch (sysclk_conf & 0x0f) {
 226         case QIXIS_SYSCLK_64:
 227                 return 64000000;
 228         case QIXIS_SYSCLK_83:
 229                 return 83333333;
 230         case QIXIS_SYSCLK_100:
 231                 return 100000000;
 232         case QIXIS_SYSCLK_125:
 233                 return 125000000;
 234         case QIXIS_SYSCLK_133:
 235                 return 133333333;
 236         case QIXIS_SYSCLK_150:
 237                 return 150000000;
 238         case QIXIS_SYSCLK_160:
 239                 return 160000000;
 240         case QIXIS_SYSCLK_166:
 241                 return 166666666;
 242         }
 243
 244         return 66666666;
 245 }
 246
 247 unsigned long get_board_ddr_clk(void)
 248 {
 249         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 250
 251         if (if_board_diff_clk())
 252                 return get_board_sys_clk();
 253         switch ((ddrclk_conf & 0x30) >> 4) {
 254         case QIXIS_DDRCLK_100:
 255                 return 100000000;
 256         case QIXIS_DDRCLK_125:
 257                 return 125000000;
 258         case QIXIS_DDRCLK_133:
 259                 return 133333333;
 260         }
 261
 262         return 66666666;
 263 }
 264
 265 #ifdef CONFIG_LPUART
 266 u32 get_lpuart_clk(void)
 267 {
 268         return gd->bus_clk;
 269 }
 270 #endif
 271
 272 int select_i2c_ch_pca9547(u8 ch)
 273 {
 274         int ret;
 275
 276         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 277         if (ret) {
 278                 puts("PCA: failed to select proper channel\n");
 279                 return ret;
 280         }
 281
 282         return 0;
 283 }
 284
 285 int dram_init(void)
 286 {
 287         /*
 288          * When resuming from deep sleep, the I2C channel may not be
 289          * in the default channel. So, switch to the default channel
 290          * before accessing DDR SPD.
 291          */
 292         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 293         fsl_initdram();
 294 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 295         defined(CONFIG_SPL_BUILD)
 296         /* This will break-before-make MMU for DDR */
 297         update_early_mmu_table();
 298 #endif
 299
 300         return 0;
 301 }
 302
 303 int i2c_multiplexer_select_vid_channel(u8 channel)
 304 {
 305         return select_i2c_ch_pca9547(channel);
 306 }
 307
 308 int board_early_init_f(void)
 309 {
 310 #ifdef CONFIG_HAS_FSL_XHCI_USB
 311         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 312         u32 usb_pwrfault;
 313 #endif
 314 #ifdef CONFIG_LPUART
 315         u8 uart;
 316 #endif
 317
 318 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 319         i2c_early_init_f();
 320 #endif
 321         fsl_lsch2_early_init_f();
 322
 323 #ifdef CONFIG_HAS_FSL_XHCI_USB
 324         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 325         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 326         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 327                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 328                         (SCFG_USBPWRFAULT_DEDICATED <<
 329                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 330                         (SCFG_USBPWRFAULT_SHARED <<
 331                         SCFG_USBPWRFAULT_USB1_SHIFT);
 332         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 333 #endif
 334
 335 #ifdef CONFIG_LPUART
 336         /* We use lpuart0 as system console */
 337         uart = QIXIS_READ(brdcfg[14]);
 338         uart &= ~CFG_UART_MUX_MASK;
 339         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 340         QIXIS_WRITE(brdcfg[14], uart);
 341 #endif
 342
 343         return 0;
 344 }
 345
 346 #ifdef CONFIG_FSL_DEEP_SLEEP
 347 /* determine if it is a warm boot */
 348 bool is_warm_boot(void)
 349 {
 350 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 351         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 352
 353         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 354                 return 1;
 355
 356         return 0;
 357 }
 358 #endif
 359
 360 int config_board_mux(int ctrl_type)
 361 {
 362         u8 reg14;
 363
 364         reg14 = QIXIS_READ(brdcfg[14]);
 365
 366         switch (ctrl_type) {
 367         case MUX_TYPE_GPIO:
 368                 reg14 = (reg14 & (~0x6)) | 0x2;
 369                 break;
 370         default:
 371                 puts("Unsupported mux interface type\n");
 372                 return -1;
 373         }
 374
 375         QIXIS_WRITE(brdcfg[14], reg14);
 376
 377         return 0;
 378 }
 379
 380 int config_serdes_mux(void)
 381 {
 382         return 0;
 383 }
 384
 385 #ifdef CONFIG_MISC_INIT_R
 386 int misc_init_r(void)
 387 {
 388         if (hwconfig("gpio"))
 389                 config_board_mux(MUX_TYPE_GPIO);
 390
 391         return 0;
 392 }
 393 #endif
 394
 395 int board_init(void)
 396 {
 397         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 398
 399 #ifdef CONFIG_SYS_FSL_SERDES
 400         config_serdes_mux();
 401 #endif
 402
 403         if (adjust_vdd(0))
 404                 printf("Warning: Adjusting core voltage failed.\n");
 405
 406 #ifdef CONFIG_FSL_LS_PPA
 407         ppa_init();
 408 #endif
 409
 410 #ifdef CONFIG_NXP_ESBC
 411         /*
 412          * In case of Secure Boot, the IBR configures the SMMU
 413          * to allow only Secure transactions.
 414          * SMMU must be reset in bypass mode.
 415          * Set the ClientPD bit and Clear the USFCFG Bit
 416          */
 417         u32 val;
 418         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 419         out_le32(SMMU_SCR0, val);
 420         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 421         out_le32(SMMU_NSCR0, val);
 422 #endif
 423
 424 #ifdef CONFIG_FSL_CAAM
 425         sec_init();
 426 #endif
 427
 428         return 0;
 429 }
 430
 431 #ifdef CONFIG_OF_BOARD_SETUP
 432 int ft_board_setup(void *blob, bd_t *bd)
 433 {
 434         u64 base[CONFIG_NR_DRAM_BANKS];
 435         u64 size[CONFIG_NR_DRAM_BANKS];
 436         u8 reg;
 437
 438         /* fixup DT for the two DDR banks */
 439         base[0] = gd->bd->bi_dram[0].start;
 440         size[0] = gd->bd->bi_dram[0].size;
 441         base[1] = gd->bd->bi_dram[1].start;
 442         size[1] = gd->bd->bi_dram[1].size;
 443
 444         fdt_fixup_memory_banks(blob, base, size, 2);
 445         ft_cpu_setup(blob, bd);
 446
 447 #ifdef CONFIG_SYS_DPAA_FMAN
 448         fdt_fixup_fman_ethernet(blob);
 449         fdt_fixup_board_enet(blob);
 450 #endif
 451
 452         fdt_fixup_icid(blob);
 453
 454         reg = QIXIS_READ(brdcfg[0]);
 455         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 456
 457         /* Disable IFC if QSPI is enabled */
 458         if (reg == 0xF)
 459                 do_fixup_by_compat(blob, "fsl,ifc",
 460                                    "status", "disabled", 8 + 1, 1);
 461
 462         return 0;
 463 }
 464 #endif
 465
 466 u8 flash_read8(void *addr)
 467 {
 468         return __raw_readb(addr + 1);
 469 }
 470
 471 void flash_write16(u16 val, void *addr)
 472 {
 473         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 474
 475         __raw_writew(shftval, addr);
 476 }
 477
 478 u16 flash_read16(void *addr)
 479 {
 480         u16 val = __raw_readw(addr);
 481
 482         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 483 }
 484
 485 #ifdef CONFIG_TFABOOT
 486 void *env_sf_get_env_addr(void)
 487 {
 488         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 489 }
 490 #endif