board/freescale/ls1046aqds/ls1046aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/fsl_serdes.h>
  15 #include <asm/arch/ppa.h>
  16 #include <asm/arch/fdt.h>
  17 #include <asm/arch/mmu.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/soc.h>
  20 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  21 #include <ahci.h>
  22 #include <hwconfig.h>
  23 #include <mmc.h>
  24 #include <scsi.h>
  25 #include <fm_eth.h>
  26 #include <fsl_csu.h>
  27 #include <fsl_esdhc.h>
  28 #include <fsl_ifc.h>
  29 #include <fsl_sec.h>
  30 #include <spl.h>
  31
  32 #include "../common/vid.h"
  33 #include "../common/qixis.h"
  34 #include "ls1046aqds_qixis.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #ifdef CONFIG_SYS_I2C_EARLY_INIT
  39 void i2c_early_init_f(void);
  40 #endif
  41
  42 #ifdef CONFIG_TFABOOT
  43 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  44         {
  45                 "nor0",
  46                 CONFIG_SYS_NOR0_CSPR,
  47                 CONFIG_SYS_NOR0_CSPR_EXT,
  48                 CONFIG_SYS_NOR_AMASK,
  49                 CONFIG_SYS_NOR_CSOR,
  50                 {
  51                         CONFIG_SYS_NOR_FTIM0,
  52                         CONFIG_SYS_NOR_FTIM1,
  53                         CONFIG_SYS_NOR_FTIM2,
  54                         CONFIG_SYS_NOR_FTIM3
  55                 },
  56
  57         },
  58         {
  59                 "nor1",
  60                 CONFIG_SYS_NOR1_CSPR,
  61                 CONFIG_SYS_NOR1_CSPR_EXT,
  62                 CONFIG_SYS_NOR_AMASK,
  63                 CONFIG_SYS_NOR_CSOR,
  64                 {
  65                         CONFIG_SYS_NOR_FTIM0,
  66                         CONFIG_SYS_NOR_FTIM1,
  67                         CONFIG_SYS_NOR_FTIM2,
  68                         CONFIG_SYS_NOR_FTIM3
  69                 },
  70         },
  71         {
  72                 "nand",
  73                 CONFIG_SYS_NAND_CSPR,
  74                 CONFIG_SYS_NAND_CSPR_EXT,
  75                 CONFIG_SYS_NAND_AMASK,
  76                 CONFIG_SYS_NAND_CSOR,
  77                 {
  78                         CONFIG_SYS_NAND_FTIM0,
  79                         CONFIG_SYS_NAND_FTIM1,
  80                         CONFIG_SYS_NAND_FTIM2,
  81                         CONFIG_SYS_NAND_FTIM3
  82                 },
  83         },
  84         {
  85                 "fpga",
  86                 CONFIG_SYS_FPGA_CSPR,
  87                 CONFIG_SYS_FPGA_CSPR_EXT,
  88                 CONFIG_SYS_FPGA_AMASK,
  89                 CONFIG_SYS_FPGA_CSOR,
  90                 {
  91                         CONFIG_SYS_FPGA_FTIM0,
  92                         CONFIG_SYS_FPGA_FTIM1,
  93                         CONFIG_SYS_FPGA_FTIM2,
  94                         CONFIG_SYS_FPGA_FTIM3
  95                 },
  96         }
  97 };
  98
  99 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 100         {
 101                 "nand",
 102                 CONFIG_SYS_NAND_CSPR,
 103                 CONFIG_SYS_NAND_CSPR_EXT,
 104                 CONFIG_SYS_NAND_AMASK,
 105                 CONFIG_SYS_NAND_CSOR,
 106                 {
 107                         CONFIG_SYS_NAND_FTIM0,
 108                         CONFIG_SYS_NAND_FTIM1,
 109                         CONFIG_SYS_NAND_FTIM2,
 110                         CONFIG_SYS_NAND_FTIM3
 111                 },
 112         },
 113         {
 114                 "nor0",
 115                 CONFIG_SYS_NOR0_CSPR,
 116                 CONFIG_SYS_NOR0_CSPR_EXT,
 117                 CONFIG_SYS_NOR_AMASK,
 118                 CONFIG_SYS_NOR_CSOR,
 119                 {
 120                         CONFIG_SYS_NOR_FTIM0,
 121                         CONFIG_SYS_NOR_FTIM1,
 122                         CONFIG_SYS_NOR_FTIM2,
 123                         CONFIG_SYS_NOR_FTIM3
 124                 },
 125         },
 126         {
 127                 "nor1",
 128                 CONFIG_SYS_NOR1_CSPR,
 129                 CONFIG_SYS_NOR1_CSPR_EXT,
 130                 CONFIG_SYS_NOR_AMASK,
 131                 CONFIG_SYS_NOR_CSOR,
 132                 {
 133                         CONFIG_SYS_NOR_FTIM0,
 134                         CONFIG_SYS_NOR_FTIM1,
 135                         CONFIG_SYS_NOR_FTIM2,
 136                         CONFIG_SYS_NOR_FTIM3
 137                 },
 138         },
 139         {
 140                 "fpga",
 141                 CONFIG_SYS_FPGA_CSPR,
 142                 CONFIG_SYS_FPGA_CSPR_EXT,
 143                 CONFIG_SYS_FPGA_AMASK,
 144                 CONFIG_SYS_FPGA_CSOR,
 145                 {
 146                         CONFIG_SYS_FPGA_FTIM0,
 147                         CONFIG_SYS_FPGA_FTIM1,
 148                         CONFIG_SYS_FPGA_FTIM2,
 149                         CONFIG_SYS_FPGA_FTIM3
 150                 },
 151         }
 152 };
 153
 154 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 155 {
 156         enum boot_src src = get_boot_src();
 157
 158         if (src == BOOT_SOURCE_IFC_NAND)
 159                 regs_info->regs = ifc_cfg_nand_boot;
 160         else
 161                 regs_info->regs = ifc_cfg_nor_boot;
 162         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 163 }
 164
 165 #endif
 166
 167 enum {
 168         MUX_TYPE_GPIO,
 169 };
 170
 171 int checkboard(void)
 172 {
 173 #ifdef CONFIG_TFABOOT
 174         enum boot_src src = get_boot_src();
 175 #endif
 176         char buf[64];
 177 #ifndef CONFIG_SD_BOOT
 178         u8 sw;
 179 #endif
 180
 181         puts("Board: LS1046AQDS, boot from ");
 182
 183 #ifdef CONFIG_TFABOOT
 184         if (src == BOOT_SOURCE_SD_MMC)
 185                 puts("SD\n");
 186         else {
 187 #endif
 188
 189 #ifdef CONFIG_SD_BOOT
 190         puts("SD\n");
 191 #else
 192         sw = QIXIS_READ(brdcfg[0]);
 193         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 194
 195         if (sw < 0x8)
 196                 printf("vBank: %d\n", sw);
 197         else if (sw == 0x8)
 198                 puts("PromJet\n");
 199         else if (sw == 0x9)
 200                 puts("NAND\n");
 201         else if (sw == 0xF)
 202                 printf("QSPI\n");
 203         else
 204                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 205 #endif
 206
 207 #ifdef CONFIG_TFABOOT
 208         }
 209 #endif
 210         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 211                QIXIS_READ(id), QIXIS_READ(arch));
 212
 213         printf("FPGA:  v%d (%s), build %d\n",
 214                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 215                (int)qixis_read_minor());
 216
 217         return 0;
 218 }
 219
 220 bool if_board_diff_clk(void)
 221 {
 222         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 223
 224         return diff_conf & 0x40;
 225 }
 226
 227 unsigned long get_board_sys_clk(void)
 228 {
 229         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 230
 231         switch (sysclk_conf & 0x0f) {
 232         case QIXIS_SYSCLK_64:
 233                 return 64000000;
 234         case QIXIS_SYSCLK_83:
 235                 return 83333333;
 236         case QIXIS_SYSCLK_100:
 237                 return 100000000;
 238         case QIXIS_SYSCLK_125:
 239                 return 125000000;
 240         case QIXIS_SYSCLK_133:
 241                 return 133333333;
 242         case QIXIS_SYSCLK_150:
 243                 return 150000000;
 244         case QIXIS_SYSCLK_160:
 245                 return 160000000;
 246         case QIXIS_SYSCLK_166:
 247                 return 166666666;
 248         }
 249
 250         return 66666666;
 251 }
 252
 253 unsigned long get_board_ddr_clk(void)
 254 {
 255         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 256
 257         if (if_board_diff_clk())
 258                 return get_board_sys_clk();
 259         switch ((ddrclk_conf & 0x30) >> 4) {
 260         case QIXIS_DDRCLK_100:
 261                 return 100000000;
 262         case QIXIS_DDRCLK_125:
 263                 return 125000000;
 264         case QIXIS_DDRCLK_133:
 265                 return 133333333;
 266         }
 267
 268         return 66666666;
 269 }
 270
 271 #ifdef CONFIG_LPUART
 272 u32 get_lpuart_clk(void)
 273 {
 274         return gd->bus_clk;
 275 }
 276 #endif
 277
 278 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 279 {
 280         int ret;
 281 #ifdef CONFIG_DM_I2C
 282         struct udevice *dev;
 283
 284         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 285                                       1, &dev);
 286         if (ret) {
 287                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 288                        bus_num);
 289                 return ret;
 290         }
 291         ret = dm_i2c_write(dev, 0, &ch, 1);
 292 #else
 293         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 294 #endif
 295         if (ret) {
 296                 puts("PCA: failed to select proper channel\n");
 297                 return ret;
 298         }
 299
 300         return 0;
 301 }
 302
 303 int dram_init(void)
 304 {
 305         /*
 306          * When resuming from deep sleep, the I2C channel may not be
 307          * in the default channel. So, switch to the default channel
 308          * before accessing DDR SPD.
 309          *
 310          * PCA9547 mount on I2C1 bus
 311          */
 312         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 313         fsl_initdram();
 314 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 315         defined(CONFIG_SPL_BUILD)
 316         /* This will break-before-make MMU for DDR */
 317         update_early_mmu_table();
 318 #endif
 319
 320         return 0;
 321 }
 322
 323 int i2c_multiplexer_select_vid_channel(u8 channel)
 324 {
 325         return select_i2c_ch_pca9547(channel, 0);
 326 }
 327
 328 int board_early_init_f(void)
 329 {
 330         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 331 #ifdef CONFIG_HAS_FSL_XHCI_USB
 332         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 333         u32 usb_pwrfault;
 334 #endif
 335 #ifdef CONFIG_LPUART
 336         u8 uart;
 337 #endif
 338
 339         /*
 340          * Enable secure system counter for timer
 341          */
 342         out_le32(cntcr, 0x1);
 343
 344 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 345         i2c_early_init_f();
 346 #endif
 347         fsl_lsch2_early_init_f();
 348
 349 #ifdef CONFIG_HAS_FSL_XHCI_USB
 350         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 351         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 352         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 353                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 354                         (SCFG_USBPWRFAULT_DEDICATED <<
 355                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 356                         (SCFG_USBPWRFAULT_SHARED <<
 357                         SCFG_USBPWRFAULT_USB1_SHIFT);
 358         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 359 #endif
 360
 361 #ifdef CONFIG_LPUART
 362         /* We use lpuart0 as system console */
 363         uart = QIXIS_READ(brdcfg[14]);
 364         uart &= ~CFG_UART_MUX_MASK;
 365         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 366         QIXIS_WRITE(brdcfg[14], uart);
 367 #endif
 368
 369         return 0;
 370 }
 371
 372 #ifdef CONFIG_FSL_DEEP_SLEEP
 373 /* determine if it is a warm boot */
 374 bool is_warm_boot(void)
 375 {
 376 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 377         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 378
 379         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 380                 return 1;
 381
 382         return 0;
 383 }
 384 #endif
 385
 386 int config_board_mux(int ctrl_type)
 387 {
 388         u8 reg14;
 389
 390         reg14 = QIXIS_READ(brdcfg[14]);
 391
 392         switch (ctrl_type) {
 393         case MUX_TYPE_GPIO:
 394                 reg14 = (reg14 & (~0x6)) | 0x2;
 395                 break;
 396         default:
 397                 puts("Unsupported mux interface type\n");
 398                 return -1;
 399         }
 400
 401         QIXIS_WRITE(brdcfg[14], reg14);
 402
 403         return 0;
 404 }
 405
 406 int config_serdes_mux(void)
 407 {
 408         return 0;
 409 }
 410
 411 #ifdef CONFIG_MISC_INIT_R
 412 int misc_init_r(void)
 413 {
 414         if (hwconfig("gpio"))
 415                 config_board_mux(MUX_TYPE_GPIO);
 416
 417         return 0;
 418 }
 419 #endif
 420
 421 int board_init(void)
 422 {
 423         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 424
 425 #ifdef CONFIG_SYS_FSL_SERDES
 426         config_serdes_mux();
 427 #endif
 428
 429         if (adjust_vdd(0))
 430                 printf("Warning: Adjusting core voltage failed.\n");
 431
 432 #ifdef CONFIG_FSL_LS_PPA
 433         ppa_init();
 434 #endif
 435
 436 #ifdef CONFIG_NXP_ESBC
 437         /*
 438          * In case of Secure Boot, the IBR configures the SMMU
 439          * to allow only Secure transactions.
 440          * SMMU must be reset in bypass mode.
 441          * Set the ClientPD bit and Clear the USFCFG Bit
 442          */
 443         u32 val;
 444         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 445         out_le32(SMMU_SCR0, val);
 446         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 447         out_le32(SMMU_NSCR0, val);
 448 #endif
 449
 450 #ifdef CONFIG_FSL_CAAM
 451         sec_init();
 452 #endif
 453
 454         return 0;
 455 }
 456
 457 #ifdef CONFIG_OF_BOARD_SETUP
 458 int ft_board_setup(void *blob, struct bd_info *bd)
 459 {
 460         u64 base[CONFIG_NR_DRAM_BANKS];
 461         u64 size[CONFIG_NR_DRAM_BANKS];
 462         u8 reg;
 463
 464         /* fixup DT for the two DDR banks */
 465         base[0] = gd->bd->bi_dram[0].start;
 466         size[0] = gd->bd->bi_dram[0].size;
 467         base[1] = gd->bd->bi_dram[1].start;
 468         size[1] = gd->bd->bi_dram[1].size;
 469
 470         fdt_fixup_memory_banks(blob, base, size, 2);
 471         ft_cpu_setup(blob, bd);
 472
 473 #ifdef CONFIG_SYS_DPAA_FMAN
 474 #ifndef CONFIG_DM_ETH
 475         fdt_fixup_fman_ethernet(blob);
 476 #endif
 477         fdt_fixup_board_enet(blob);
 478 #endif
 479
 480         fdt_fixup_icid(blob);
 481
 482         reg = QIXIS_READ(brdcfg[0]);
 483         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 484
 485         /* Disable IFC if QSPI is enabled */
 486         if (reg == 0xF)
 487                 do_fixup_by_compat(blob, "fsl,ifc",
 488                                    "status", "disabled", 8 + 1, 1);
 489
 490         return 0;
 491 }
 492 #endif
 493
 494 u8 flash_read8(void *addr)
 495 {
 496         return __raw_readb(addr + 1);
 497 }
 498
 499 void flash_write16(u16 val, void *addr)
 500 {
 501         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 502
 503         __raw_writew(shftval, addr);
 504 }
 505
 506 u16 flash_read16(void *addr)
 507 {
 508         u16 val = __raw_readw(addr);
 509
 510         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 511 }
 512
 513 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 514 void *env_sf_get_env_addr(void)
 515 {
 516         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 517 }
 518 #endif