board/freescale/ls1046aqds/ls1046aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/ppa.h>
  17 #include <asm/arch/fdt.h>
  18 #include <asm/arch/mmu.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/soc.h>
  21 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  22 #include <ahci.h>
  23 #include <hwconfig.h>
  24 #include <mmc.h>
  25 #include <scsi.h>
  26 #include <fm_eth.h>
  27 #include <fsl_csu.h>
  28 #include <fsl_esdhc.h>
  29 #include <fsl_ifc.h>
  30 #include <fsl_sec.h>
  31 #include <spl.h>
  32 #include "../common/i2c_mux.h"
  33
  34 #include "../common/vid.h"
  35 #include "../common/qixis.h"
  36 #include "ls1046aqds_qixis.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #ifdef CONFIG_SYS_I2C_EARLY_INIT
  41 void i2c_early_init_f(void);
  42 #endif
  43
  44 #ifdef CONFIG_TFABOOT
  45 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  46         {
  47                 "nor0",
  48                 CONFIG_SYS_NOR0_CSPR,
  49                 CONFIG_SYS_NOR0_CSPR_EXT,
  50                 CONFIG_SYS_NOR_AMASK,
  51                 CONFIG_SYS_NOR_CSOR,
  52                 {
  53                         CONFIG_SYS_NOR_FTIM0,
  54                         CONFIG_SYS_NOR_FTIM1,
  55                         CONFIG_SYS_NOR_FTIM2,
  56                         CONFIG_SYS_NOR_FTIM3
  57                 },
  58
  59         },
  60         {
  61                 "nor1",
  62                 CONFIG_SYS_NOR1_CSPR,
  63                 CONFIG_SYS_NOR1_CSPR_EXT,
  64                 CONFIG_SYS_NOR_AMASK,
  65                 CONFIG_SYS_NOR_CSOR,
  66                 {
  67                         CONFIG_SYS_NOR_FTIM0,
  68                         CONFIG_SYS_NOR_FTIM1,
  69                         CONFIG_SYS_NOR_FTIM2,
  70                         CONFIG_SYS_NOR_FTIM3
  71                 },
  72         },
  73         {
  74                 "nand",
  75                 CONFIG_SYS_NAND_CSPR,
  76                 CONFIG_SYS_NAND_CSPR_EXT,
  77                 CONFIG_SYS_NAND_AMASK,
  78                 CONFIG_SYS_NAND_CSOR,
  79                 {
  80                         CONFIG_SYS_NAND_FTIM0,
  81                         CONFIG_SYS_NAND_FTIM1,
  82                         CONFIG_SYS_NAND_FTIM2,
  83                         CONFIG_SYS_NAND_FTIM3
  84                 },
  85         },
  86         {
  87                 "fpga",
  88                 CONFIG_SYS_FPGA_CSPR,
  89                 CONFIG_SYS_FPGA_CSPR_EXT,
  90                 CONFIG_SYS_FPGA_AMASK,
  91                 CONFIG_SYS_FPGA_CSOR,
  92                 {
  93                         CONFIG_SYS_FPGA_FTIM0,
  94                         CONFIG_SYS_FPGA_FTIM1,
  95                         CONFIG_SYS_FPGA_FTIM2,
  96                         CONFIG_SYS_FPGA_FTIM3
  97                 },
  98         }
  99 };
 100
 101 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 102         {
 103                 "nand",
 104                 CONFIG_SYS_NAND_CSPR,
 105                 CONFIG_SYS_NAND_CSPR_EXT,
 106                 CONFIG_SYS_NAND_AMASK,
 107                 CONFIG_SYS_NAND_CSOR,
 108                 {
 109                         CONFIG_SYS_NAND_FTIM0,
 110                         CONFIG_SYS_NAND_FTIM1,
 111                         CONFIG_SYS_NAND_FTIM2,
 112                         CONFIG_SYS_NAND_FTIM3
 113                 },
 114         },
 115         {
 116                 "nor0",
 117                 CONFIG_SYS_NOR0_CSPR,
 118                 CONFIG_SYS_NOR0_CSPR_EXT,
 119                 CONFIG_SYS_NOR_AMASK,
 120                 CONFIG_SYS_NOR_CSOR,
 121                 {
 122                         CONFIG_SYS_NOR_FTIM0,
 123                         CONFIG_SYS_NOR_FTIM1,
 124                         CONFIG_SYS_NOR_FTIM2,
 125                         CONFIG_SYS_NOR_FTIM3
 126                 },
 127         },
 128         {
 129                 "nor1",
 130                 CONFIG_SYS_NOR1_CSPR,
 131                 CONFIG_SYS_NOR1_CSPR_EXT,
 132                 CONFIG_SYS_NOR_AMASK,
 133                 CONFIG_SYS_NOR_CSOR,
 134                 {
 135                         CONFIG_SYS_NOR_FTIM0,
 136                         CONFIG_SYS_NOR_FTIM1,
 137                         CONFIG_SYS_NOR_FTIM2,
 138                         CONFIG_SYS_NOR_FTIM3
 139                 },
 140         },
 141         {
 142                 "fpga",
 143                 CONFIG_SYS_FPGA_CSPR,
 144                 CONFIG_SYS_FPGA_CSPR_EXT,
 145                 CONFIG_SYS_FPGA_AMASK,
 146                 CONFIG_SYS_FPGA_CSOR,
 147                 {
 148                         CONFIG_SYS_FPGA_FTIM0,
 149                         CONFIG_SYS_FPGA_FTIM1,
 150                         CONFIG_SYS_FPGA_FTIM2,
 151                         CONFIG_SYS_FPGA_FTIM3
 152                 },
 153         }
 154 };
 155
 156 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 157 {
 158         enum boot_src src = get_boot_src();
 159
 160         if (src == BOOT_SOURCE_IFC_NAND)
 161                 regs_info->regs = ifc_cfg_nand_boot;
 162         else
 163                 regs_info->regs = ifc_cfg_nor_boot;
 164         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 165 }
 166
 167 #endif
 168
 169 enum {
 170         MUX_TYPE_GPIO,
 171 };
 172
 173 int checkboard(void)
 174 {
 175 #ifdef CONFIG_TFABOOT
 176         enum boot_src src = get_boot_src();
 177 #endif
 178         char buf[64];
 179 #ifndef CONFIG_SD_BOOT
 180         u8 sw;
 181 #endif
 182
 183         puts("Board: LS1046AQDS, boot from ");
 184
 185 #ifdef CONFIG_TFABOOT
 186         if (src == BOOT_SOURCE_SD_MMC)
 187                 puts("SD\n");
 188         else {
 189 #endif
 190
 191 #ifdef CONFIG_SD_BOOT
 192         puts("SD\n");
 193 #else
 194         sw = QIXIS_READ(brdcfg[0]);
 195         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 196
 197         if (sw < 0x8)
 198                 printf("vBank: %d\n", sw);
 199         else if (sw == 0x8)
 200                 puts("PromJet\n");
 201         else if (sw == 0x9)
 202                 puts("NAND\n");
 203         else if (sw == 0xF)
 204                 printf("QSPI\n");
 205         else
 206                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 207 #endif
 208
 209 #ifdef CONFIG_TFABOOT
 210         }
 211 #endif
 212         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 213                QIXIS_READ(id), QIXIS_READ(arch));
 214
 215         printf("FPGA:  v%d (%s), build %d\n",
 216                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 217                (int)qixis_read_minor());
 218
 219         return 0;
 220 }
 221
 222 bool if_board_diff_clk(void)
 223 {
 224         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 225
 226         return diff_conf & 0x40;
 227 }
 228
 229 unsigned long get_board_sys_clk(void)
 230 {
 231         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 232
 233         switch (sysclk_conf & 0x0f) {
 234         case QIXIS_SYSCLK_64:
 235                 return 64000000;
 236         case QIXIS_SYSCLK_83:
 237                 return 83333333;
 238         case QIXIS_SYSCLK_100:
 239                 return 100000000;
 240         case QIXIS_SYSCLK_125:
 241                 return 125000000;
 242         case QIXIS_SYSCLK_133:
 243                 return 133333333;
 244         case QIXIS_SYSCLK_150:
 245                 return 150000000;
 246         case QIXIS_SYSCLK_160:
 247                 return 160000000;
 248         case QIXIS_SYSCLK_166:
 249                 return 166666666;
 250         }
 251
 252         return 66666666;
 253 }
 254
 255 unsigned long get_board_ddr_clk(void)
 256 {
 257         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 258
 259         if (if_board_diff_clk())
 260                 return get_board_sys_clk();
 261         switch ((ddrclk_conf & 0x30) >> 4) {
 262         case QIXIS_DDRCLK_100:
 263                 return 100000000;
 264         case QIXIS_DDRCLK_125:
 265                 return 125000000;
 266         case QIXIS_DDRCLK_133:
 267                 return 133333333;
 268         }
 269
 270         return 66666666;
 271 }
 272
 273 #ifdef CONFIG_LPUART
 274 u32 get_lpuart_clk(void)
 275 {
 276         return gd->bus_clk;
 277 }
 278 #endif
 279
 280 int dram_init(void)
 281 {
 282         /*
 283          * When resuming from deep sleep, the I2C channel may not be
 284          * in the default channel. So, switch to the default channel
 285          * before accessing DDR SPD.
 286          *
 287          * PCA9547 mount on I2C1 bus
 288          */
 289         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 290         fsl_initdram();
 291 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 292         defined(CONFIG_SPL_BUILD)
 293         /* This will break-before-make MMU for DDR */
 294         update_early_mmu_table();
 295 #endif
 296
 297         return 0;
 298 }
 299
 300 int i2c_multiplexer_select_vid_channel(u8 channel)
 301 {
 302         return select_i2c_ch_pca9547(channel, 0);
 303 }
 304
 305 int board_early_init_f(void)
 306 {
 307         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 308 #ifdef CONFIG_HAS_FSL_XHCI_USB
 309         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 310         u32 usb_pwrfault;
 311 #endif
 312 #ifdef CONFIG_LPUART
 313         u8 uart;
 314 #endif
 315
 316         /*
 317          * Enable secure system counter for timer
 318          */
 319         out_le32(cntcr, 0x1);
 320
 321 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 322         i2c_early_init_f();
 323 #endif
 324         fsl_lsch2_early_init_f();
 325
 326 #ifdef CONFIG_HAS_FSL_XHCI_USB
 327         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 328         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 329         usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 330                         SCFG_USBPWRFAULT_USB3_SHIFT) |
 331                         (SCFG_USBPWRFAULT_DEDICATED <<
 332                         SCFG_USBPWRFAULT_USB2_SHIFT) |
 333                         (SCFG_USBPWRFAULT_SHARED <<
 334                         SCFG_USBPWRFAULT_USB1_SHIFT);
 335         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 336 #endif
 337
 338 #ifdef CONFIG_LPUART
 339         /* We use lpuart0 as system console */
 340         uart = QIXIS_READ(brdcfg[14]);
 341         uart &= ~CFG_UART_MUX_MASK;
 342         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 343         QIXIS_WRITE(brdcfg[14], uart);
 344 #endif
 345
 346         return 0;
 347 }
 348
 349 #ifdef CONFIG_FSL_DEEP_SLEEP
 350 /* determine if it is a warm boot */
 351 bool is_warm_boot(void)
 352 {
 353 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 354         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 355
 356         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 357                 return 1;
 358
 359         return 0;
 360 }
 361 #endif
 362
 363 int config_board_mux(int ctrl_type)
 364 {
 365         u8 reg14;
 366
 367         reg14 = QIXIS_READ(brdcfg[14]);
 368
 369         switch (ctrl_type) {
 370         case MUX_TYPE_GPIO:
 371                 reg14 = (reg14 & (~0x6)) | 0x2;
 372                 break;
 373         default:
 374                 puts("Unsupported mux interface type\n");
 375                 return -1;
 376         }
 377
 378         QIXIS_WRITE(brdcfg[14], reg14);
 379
 380         return 0;
 381 }
 382
 383 int config_serdes_mux(void)
 384 {
 385         return 0;
 386 }
 387
 388 #ifdef CONFIG_MISC_INIT_R
 389 int misc_init_r(void)
 390 {
 391         if (hwconfig("gpio"))
 392                 config_board_mux(MUX_TYPE_GPIO);
 393
 394         return 0;
 395 }
 396 #endif
 397
 398 int board_init(void)
 399 {
 400         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 401
 402 #ifdef CONFIG_SYS_FSL_SERDES
 403         config_serdes_mux();
 404 #endif
 405
 406         if (adjust_vdd(0))
 407                 printf("Warning: Adjusting core voltage failed.\n");
 408
 409 #ifdef CONFIG_FSL_LS_PPA
 410         ppa_init();
 411 #endif
 412
 413 #ifdef CONFIG_NXP_ESBC
 414         /*
 415          * In case of Secure Boot, the IBR configures the SMMU
 416          * to allow only Secure transactions.
 417          * SMMU must be reset in bypass mode.
 418          * Set the ClientPD bit and Clear the USFCFG Bit
 419          */
 420         u32 val;
 421         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 422         out_le32(SMMU_SCR0, val);
 423         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 424         out_le32(SMMU_NSCR0, val);
 425 #endif
 426
 427 #ifdef CONFIG_FSL_CAAM
 428         sec_init();
 429 #endif
 430
 431         return 0;
 432 }
 433
 434 #ifdef CONFIG_OF_BOARD_SETUP
 435 int ft_board_setup(void *blob, struct bd_info *bd)
 436 {
 437         u64 base[CONFIG_NR_DRAM_BANKS];
 438         u64 size[CONFIG_NR_DRAM_BANKS];
 439         u8 reg;
 440
 441         /* fixup DT for the two DDR banks */
 442         base[0] = gd->bd->bi_dram[0].start;
 443         size[0] = gd->bd->bi_dram[0].size;
 444         base[1] = gd->bd->bi_dram[1].start;
 445         size[1] = gd->bd->bi_dram[1].size;
 446
 447         fdt_fixup_memory_banks(blob, base, size, 2);
 448         ft_cpu_setup(blob, bd);
 449
 450 #ifdef CONFIG_SYS_DPAA_FMAN
 451 #ifndef CONFIG_DM_ETH
 452         fdt_fixup_fman_ethernet(blob);
 453 #endif
 454         fdt_fixup_board_enet(blob);
 455 #endif
 456
 457         fdt_fixup_icid(blob);
 458
 459         reg = QIXIS_READ(brdcfg[0]);
 460         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 461
 462         /* Disable IFC if QSPI is enabled */
 463         if (reg == 0xF)
 464                 do_fixup_by_compat(blob, "fsl,ifc",
 465                                    "status", "disabled", 8 + 1, 1);
 466
 467         return 0;
 468 }
 469 #endif
 470
 471 u8 flash_read8(void *addr)
 472 {
 473         return __raw_readb(addr + 1);
 474 }
 475
 476 void flash_write16(u16 val, void *addr)
 477 {
 478         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 479
 480         __raw_writew(shftval, addr);
 481 }
 482
 483 u16 flash_read16(void *addr)
 484 {
 485         u16 val = __raw_readw(addr);
 486
 487         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 488 }
 489
 490 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 491 void *env_sf_get_env_addr(void)
 492 {
 493         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 494 }
 495 #endif