1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019, 2021 NXP
8 #include <fdt_support.h>
10 #include <asm/global_data.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch-fsl-layerscape/fsl_icid.h>
22 #include <fsl_esdhc.h>
24 #include "../common/i2c_mux.h"
26 #define LS1046A_PORSR1_REG 0x1EE0000
27 #define BOOT_SRC_SD 0x20000000
28 #define BOOT_SRC_MASK 0xFF800000
29 #define BOARD_REV_GPIO_SHIFT 17
30 #define BOARD_REV_MASK 0x03
31 #define USB2_SEL_MASK 0x00000100
33 #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
34 (((word) & 0x00ff0000) >> 8) | \
35 (((word) & 0x0000ff00) << 8) | \
36 (((word) & 0x000000ff) << 24))
37 #define SPI_MCR_REG 0x2100000
39 DECLARE_GLOBAL_DATA_PTR;
41 static inline void demux_select_usb2(void)
44 struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
46 val = in_be32(&pgpio->gpdir);
48 out_be32(&pgpio->gpdir, val);
50 val = in_be32(&pgpio->gpdat);
52 out_be32(&pgpio->gpdat, val);
55 static inline void set_spi_cs_signal_inactive(void)
57 /* default: all CS signals inactive state is high */
59 uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
60 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
62 mcr_val = in_be32(SPI_MCR_REG);
63 mcr_val |= DSPI_MCR_HALT;
64 out_be32(SPI_MCR_REG, mcr_val);
65 out_be32(SPI_MCR_REG, mcr_cfg_val);
66 mcr_val = in_be32(SPI_MCR_REG);
67 mcr_val &= ~DSPI_MCR_HALT;
68 out_be32(SPI_MCR_REG, mcr_val);
71 int board_early_init_f(void)
73 fsl_lsch2_early_init_f();
78 static inline uint8_t get_board_version(void)
80 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
82 /* GPIO 13 and GPIO 14 are used for Board Rev */
83 u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
86 /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
87 u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
94 static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
98 rev = get_board_version();
101 puts("Board: LS1046AFRWY, Rev: A, boot from ");
104 puts("Board: LS1046AFRWY, Rev: B, boot from ");
107 puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
110 boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
112 if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
116 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
123 #ifdef CONFIG_NXP_ESBC
125 * In case of Secure Boot, the IBR configures the SMMU
126 * to allow only Secure transactions.
127 * SMMU must be reset in bypass mode.
128 * Set the ClientPD bit and Clear the USFCFG Bit
131 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
132 out_le32(SMMU_SCR0, val);
133 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
134 out_le32(SMMU_NSCR0, val);
137 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
141 int board_setup_core_volt(u32 vdd)
146 void config_board_mux(void)
148 #ifdef CONFIG_HAS_FSL_XHCI_USB
149 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
152 * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
153 * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
155 out_be32(&scfg->rcwpmuxcr0, 0x3300);
156 #ifdef CONFIG_HAS_FSL_IIC3
157 /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
158 out_be32(&scfg->rcwpmuxcr0, 0x0000);
160 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
161 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
162 SCFG_USBPWRFAULT_USB3_SHIFT) |
163 (SCFG_USBPWRFAULT_DEDICATED <<
164 SCFG_USBPWRFAULT_USB2_SHIFT) |
165 (SCFG_USBPWRFAULT_SHARED <<
166 SCFG_USBPWRFAULT_USB1_SHIFT);
167 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
168 #ifndef CONFIG_HAS_FSL_IIC3
170 * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
171 * to select I2C3_USB2_SEL_IO
172 * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
173 * I2C3 header (default)
174 * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
176 * programmed to select USB2 by setting GPIO3_23 output to one
181 set_spi_cs_signal_inactive();
184 #ifdef CONFIG_MISC_INIT_R
185 int misc_init_r(void)
192 int ft_board_setup(void *blob, struct bd_info *bd)
194 u64 base[CONFIG_NR_DRAM_BANKS];
195 u64 size[CONFIG_NR_DRAM_BANKS];
197 /* fixup DT for the two DDR banks */
198 base[0] = gd->bd->bi_dram[0].start;
199 size[0] = gd->bd->bi_dram[0].size;
200 base[1] = gd->bd->bi_dram[1].start;
201 size[1] = gd->bd->bi_dram[1].size;
203 fdt_fixup_memory_banks(blob, base, size, 2);
204 ft_cpu_setup(blob, bd);
206 #ifdef CONFIG_SYS_DPAA_FMAN
207 #ifndef CONFIG_DM_ETH
208 fdt_fixup_fman_ethernet(blob);
212 fdt_fixup_icid(blob);