1 // SPDX-License-Identifier: GPL-2.0+
8 #include <fdt_support.h>
10 #include <asm/global_data.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch-fsl-layerscape/fsl_icid.h>
22 #include <fsl_esdhc.h>
25 #include "../common/i2c_mux.h"
27 #define LS1046A_PORSR1_REG 0x1EE0000
28 #define BOOT_SRC_SD 0x20000000
29 #define BOOT_SRC_MASK 0xFF800000
30 #define BOARD_REV_GPIO_SHIFT 17
31 #define BOARD_REV_MASK 0x03
32 #define USB2_SEL_MASK 0x00000100
34 #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
35 (((word) & 0x00ff0000) >> 8) | \
36 (((word) & 0x0000ff00) << 8) | \
37 (((word) & 0x000000ff) << 24))
38 #define SPI_MCR_REG 0x2100000
40 DECLARE_GLOBAL_DATA_PTR;
42 static inline void demux_select_usb2(void)
45 struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
47 val = in_be32(&pgpio->gpdir);
49 out_be32(&pgpio->gpdir, val);
51 val = in_be32(&pgpio->gpdat);
53 out_be32(&pgpio->gpdat, val);
56 static inline void set_spi_cs_signal_inactive(void)
58 /* default: all CS signals inactive state is high */
60 uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
61 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
63 mcr_val = in_be32(SPI_MCR_REG);
64 mcr_val |= DSPI_MCR_HALT;
65 out_be32(SPI_MCR_REG, mcr_val);
66 out_be32(SPI_MCR_REG, mcr_cfg_val);
67 mcr_val = in_be32(SPI_MCR_REG);
68 mcr_val &= ~DSPI_MCR_HALT;
69 out_be32(SPI_MCR_REG, mcr_val);
72 int board_early_init_f(void)
74 fsl_lsch2_early_init_f();
79 static inline uint8_t get_board_version(void)
81 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
83 /* GPIO 13 and GPIO 14 are used for Board Rev */
84 u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
87 /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
88 u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
95 static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
99 rev = get_board_version();
102 puts("Board: LS1046AFRWY, Rev: A, boot from ");
105 puts("Board: LS1046AFRWY, Rev: B, boot from ");
108 puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
111 boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
113 if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
117 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
124 #ifdef CONFIG_NXP_ESBC
126 * In case of Secure Boot, the IBR configures the SMMU
127 * to allow only Secure transactions.
128 * SMMU must be reset in bypass mode.
129 * Set the ClientPD bit and Clear the USFCFG Bit
132 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
133 out_le32(SMMU_SCR0, val);
134 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
135 out_le32(SMMU_NSCR0, val);
138 #ifdef CONFIG_FSL_CAAM
142 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
146 int board_setup_core_volt(u32 vdd)
151 void config_board_mux(void)
153 #ifdef CONFIG_HAS_FSL_XHCI_USB
154 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
157 * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
158 * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
160 out_be32(&scfg->rcwpmuxcr0, 0x3300);
161 #ifdef CONFIG_HAS_FSL_IIC3
162 /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
163 out_be32(&scfg->rcwpmuxcr0, 0x0000);
165 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
166 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
167 SCFG_USBPWRFAULT_USB3_SHIFT) |
168 (SCFG_USBPWRFAULT_DEDICATED <<
169 SCFG_USBPWRFAULT_USB2_SHIFT) |
170 (SCFG_USBPWRFAULT_SHARED <<
171 SCFG_USBPWRFAULT_USB1_SHIFT);
172 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
173 #ifndef CONFIG_HAS_FSL_IIC3
175 * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
176 * to select I2C3_USB2_SEL_IO
177 * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
178 * I2C3 header (default)
179 * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
181 * programmed to select USB2 by setting GPIO3_23 output to one
186 set_spi_cs_signal_inactive();
189 #ifdef CONFIG_MISC_INIT_R
190 int misc_init_r(void)
197 int ft_board_setup(void *blob, struct bd_info *bd)
199 u64 base[CONFIG_NR_DRAM_BANKS];
200 u64 size[CONFIG_NR_DRAM_BANKS];
202 /* fixup DT for the two DDR banks */
203 base[0] = gd->bd->bi_dram[0].start;
204 size[0] = gd->bd->bi_dram[0].size;
205 base[1] = gd->bd->bi_dram[1].start;
206 size[1] = gd->bd->bi_dram[1].size;
208 fdt_fixup_memory_banks(blob, base, size, 2);
209 ft_cpu_setup(blob, bd);
211 #ifdef CONFIG_SYS_DPAA_FMAN
212 #ifndef CONFIG_DM_ETH
213 fdt_fixup_fman_ethernet(blob);
217 fdt_fixup_icid(blob);