1 // SPDX-License-Identifier: GPL-2.0+
8 #include <fdt_support.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <asm/arch-fsl-layerscape/fsl_icid.h>
20 #include <fsl_esdhc.h>
24 #define LS1046A_PORSR1_REG 0x1EE0000
25 #define BOOT_SRC_SD 0x20000000
26 #define BOOT_SRC_MASK 0xFF800000
27 #define BOARD_REV_GPIO_SHIFT 17
28 #define BOARD_REV_MASK 0x03
29 #define USB2_SEL_MASK 0x00000100
31 #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
32 (((word) & 0x00ff0000) >> 8) | \
33 (((word) & 0x0000ff00) << 8) | \
34 (((word) & 0x000000ff) << 24))
35 #define SPI_MCR_REG 0x2100000
37 DECLARE_GLOBAL_DATA_PTR;
39 int select_i2c_ch_pca9547(u8 ch, int bus_num)
46 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
49 printf("%s: Cannot find udev for a bus %d\n", __func__,
53 ret = dm_i2c_write(dev, 0, &ch, 1);
55 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
58 puts("PCA: failed to select proper channel\n");
65 static inline void demux_select_usb2(void)
68 struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
70 val = in_be32(&pgpio->gpdir);
72 out_be32(&pgpio->gpdir, val);
74 val = in_be32(&pgpio->gpdat);
76 out_be32(&pgpio->gpdat, val);
79 static inline void set_spi_cs_signal_inactive(void)
81 /* default: all CS signals inactive state is high */
83 uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
84 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
86 mcr_val = in_be32(SPI_MCR_REG);
87 mcr_val |= DSPI_MCR_HALT;
88 out_be32(SPI_MCR_REG, mcr_val);
89 out_be32(SPI_MCR_REG, mcr_cfg_val);
90 mcr_val = in_be32(SPI_MCR_REG);
91 mcr_val &= ~DSPI_MCR_HALT;
92 out_be32(SPI_MCR_REG, mcr_val);
95 int board_early_init_f(void)
97 fsl_lsch2_early_init_f();
102 static inline uint8_t get_board_version(void)
104 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
106 /* GPIO 13 and GPIO 14 are used for Board Rev */
107 u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
110 /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
111 u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
118 static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
122 rev = get_board_version();
125 puts("Board: LS1046AFRWY, Rev: A, boot from ");
128 puts("Board: LS1046AFRWY, Rev: B, boot from ");
131 puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
134 boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
136 if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
140 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
147 #ifdef CONFIG_NXP_ESBC
149 * In case of Secure Boot, the IBR configures the SMMU
150 * to allow only Secure transactions.
151 * SMMU must be reset in bypass mode.
152 * Set the ClientPD bit and Clear the USFCFG Bit
155 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
156 out_le32(SMMU_SCR0, val);
157 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
158 out_le32(SMMU_NSCR0, val);
161 #ifdef CONFIG_FSL_CAAM
165 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
169 int board_setup_core_volt(u32 vdd)
174 void config_board_mux(void)
176 #ifdef CONFIG_HAS_FSL_XHCI_USB
177 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
180 * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
181 * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
183 out_be32(&scfg->rcwpmuxcr0, 0x3300);
184 #ifdef CONFIG_HAS_FSL_IIC3
185 /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
186 out_be32(&scfg->rcwpmuxcr0, 0x0000);
188 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
189 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
190 SCFG_USBPWRFAULT_USB3_SHIFT) |
191 (SCFG_USBPWRFAULT_DEDICATED <<
192 SCFG_USBPWRFAULT_USB2_SHIFT) |
193 (SCFG_USBPWRFAULT_SHARED <<
194 SCFG_USBPWRFAULT_USB1_SHIFT);
195 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
196 #ifndef CONFIG_HAS_FSL_IIC3
198 * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
199 * to select I2C3_USB2_SEL_IO
200 * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
201 * I2C3 header (default)
202 * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
204 * programmed to select USB2 by setting GPIO3_23 output to one
209 set_spi_cs_signal_inactive();
212 #ifdef CONFIG_MISC_INIT_R
213 int misc_init_r(void)
220 int ft_board_setup(void *blob, bd_t *bd)
222 u64 base[CONFIG_NR_DRAM_BANKS];
223 u64 size[CONFIG_NR_DRAM_BANKS];
225 /* fixup DT for the two DDR banks */
226 base[0] = gd->bd->bi_dram[0].start;
227 size[0] = gd->bd->bi_dram[0].size;
228 base[1] = gd->bd->bi_dram[1].start;
229 size[1] = gd->bd->bi_dram[1].size;
231 fdt_fixup_memory_banks(blob, base, size, 2);
232 ft_cpu_setup(blob, bd);
234 #ifdef CONFIG_SYS_DPAA_FMAN
235 #ifndef CONFIG_DM_ETH
236 fdt_fixup_fman_ethernet(blob);
240 fdt_fixup_icid(blob);