2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
19 #include <fsl_esdhc.h>
21 #include <environment.h>
29 DECLARE_GLOBAL_DATA_PTR;
33 static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
34 #ifndef CONFIG_SD_BOOT
35 u8 cfg_rcw_src1, cfg_rcw_src2;
40 printf("Board: LS1043ARDB, boot from ");
45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
47 cpld_rev_bit(&cfg_rcw_src1);
48 cfg_rcw_src = cfg_rcw_src1;
49 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
51 if (cfg_rcw_src == 0x25)
52 printf("vBank %d\n", CPLD_READ(vbank));
53 else if (cfg_rcw_src == 0x106)
56 printf("Invalid setting of SW4\n");
59 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
60 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
62 puts("SERDES Reference Clocks:\n");
63 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
64 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
71 gd->ram_size = initdram(0);
76 int board_early_init_f(void)
78 fsl_lsch2_early_init_f();
85 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
88 * Set CCI-400 control override register to enable barrier
91 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
94 init_final_memctl_regs();
97 #ifdef CONFIG_ENV_IS_NOWHERE
98 gd->env_addr = (ulong)&default_environment[0];
101 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
102 enable_layerscape_ns_access();
112 int config_board_mux(void)
114 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
117 if (hwconfig("qe-hdlc")) {
118 out_be32(&scfg->rcwpmuxcr0,
119 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
120 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
121 in_be32(&scfg->rcwpmuxcr0));
123 #ifdef CONFIG_HAS_FSL_XHCI_USB
124 out_be32(&scfg->rcwpmuxcr0, 0x3333);
125 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
126 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
127 SCFG_USBPWRFAULT_USB3_SHIFT) |
128 (SCFG_USBPWRFAULT_DEDICATED <<
129 SCFG_USBPWRFAULT_USB2_SHIFT) |
130 (SCFG_USBPWRFAULT_SHARED <<
131 SCFG_USBPWRFAULT_USB1_SHIFT);
132 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
138 #if defined(CONFIG_MISC_INIT_R)
139 int misc_init_r(void)
142 #ifdef CONFIG_SECURE_BOOT
143 /* In case of Secure Boot, the IBR configures the SMMU
144 * to allow only Secure transactions.
145 * SMMU must be reset in bypass mode.
146 * Set the ClientPD bit and Clear the USFCFG Bit
149 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
150 out_le32(SMMU_SCR0, val);
151 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
152 out_le32(SMMU_NSCR0, val);
154 #ifdef CONFIG_FSL_CAAM
161 void fdt_del_qe(void *blob)
165 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
167 fdt_del_node(blob, nodeoff);
171 int ft_board_setup(void *blob, bd_t *bd)
173 u64 base[CONFIG_NR_DRAM_BANKS];
174 u64 size[CONFIG_NR_DRAM_BANKS];
176 /* fixup DT for the two DDR banks */
177 base[0] = gd->bd->bi_dram[0].start;
178 size[0] = gd->bd->bi_dram[0].size;
179 base[1] = gd->bd->bi_dram[1].start;
180 size[1] = gd->bd->bi_dram[1].size;
182 fdt_fixup_memory_banks(blob, base, size, 2);
183 ft_cpu_setup(blob, bd);
185 #ifdef CONFIG_SYS_DPAA_FMAN
186 fdt_fixup_fman_ethernet(blob);
190 * qe-hdlc and usb multi-use the pins,
191 * when set hwconfig to qe-hdlc, delete usb node.
193 if (hwconfig("qe-hdlc"))
194 #ifdef CONFIG_HAS_FSL_XHCI_USB
195 fdt_del_node_and_alias(blob, "usb1");
198 * qe just support qe-uart and qe-hdlc,
199 * if qe-uart and qe-hdlc are not set in hwconfig,
202 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
208 u8 flash_read8(void *addr)
210 return __raw_readb(addr + 1);
213 void flash_write16(u16 val, void *addr)
215 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
217 __raw_writew(shftval, addr);
220 u16 flash_read16(void *addr)
222 u16 val = __raw_readw(addr);
224 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);