board/freescale/ls1043ardb/ls1043ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <asm/arch/soc.h>
  13 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  14 #include <fdt_support.h>
  15 #include <hwconfig.h>
  16 #include <ahci.h>
  17 #include <mmc.h>
  18 #include <scsi.h>
  19 #include <fm_eth.h>
  20 #include <fsl_esdhc.h>
  21 #include <fsl_ifc.h>
  22 #include <fsl_sec.h>
  23 #include "cpld.h"
  24 #ifdef CONFIG_U_QE
  25 #include <fsl_qe.h>
  26 #endif
  27 #include <asm/arch/ppa.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #ifdef CONFIG_TFABOOT
  32 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  33         {
  34                 "nor",
  35                 CONFIG_SYS_NOR_CSPR,
  36                 CONFIG_SYS_NOR_CSPR_EXT,
  37                 CONFIG_SYS_NOR_AMASK,
  38                 CONFIG_SYS_NOR_CSOR,
  39                 {
  40                         CONFIG_SYS_NOR_FTIM0,
  41                         CONFIG_SYS_NOR_FTIM1,
  42                         CONFIG_SYS_NOR_FTIM2,
  43                         CONFIG_SYS_NOR_FTIM3
  44                 },
  45
  46         },
  47         {
  48                 "nand",
  49                 CONFIG_SYS_NAND_CSPR,
  50                 CONFIG_SYS_NAND_CSPR_EXT,
  51                 CONFIG_SYS_NAND_AMASK,
  52                 CONFIG_SYS_NAND_CSOR,
  53                 {
  54                         CONFIG_SYS_NAND_FTIM0,
  55                         CONFIG_SYS_NAND_FTIM1,
  56                         CONFIG_SYS_NAND_FTIM2,
  57                         CONFIG_SYS_NAND_FTIM3
  58                 },
  59         },
  60         {
  61                 "cpld",
  62                 CONFIG_SYS_CPLD_CSPR,
  63                 CONFIG_SYS_CPLD_CSPR_EXT,
  64                 CONFIG_SYS_CPLD_AMASK,
  65                 CONFIG_SYS_CPLD_CSOR,
  66                 {
  67                         CONFIG_SYS_CPLD_FTIM0,
  68                         CONFIG_SYS_CPLD_FTIM1,
  69                         CONFIG_SYS_CPLD_FTIM2,
  70                         CONFIG_SYS_CPLD_FTIM3
  71                 },
  72         }
  73 };
  74
  75 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  76         {
  77                 "nand",
  78                 CONFIG_SYS_NAND_CSPR,
  79                 CONFIG_SYS_NAND_CSPR_EXT,
  80                 CONFIG_SYS_NAND_AMASK,
  81                 CONFIG_SYS_NAND_CSOR,
  82                 {
  83                         CONFIG_SYS_NAND_FTIM0,
  84                         CONFIG_SYS_NAND_FTIM1,
  85                         CONFIG_SYS_NAND_FTIM2,
  86                         CONFIG_SYS_NAND_FTIM3
  87                 },
  88         },
  89         {
  90                 "nor",
  91                 CONFIG_SYS_NOR_CSPR,
  92                 CONFIG_SYS_NOR_CSPR_EXT,
  93                 CONFIG_SYS_NOR_AMASK,
  94                 CONFIG_SYS_NOR_CSOR,
  95                 {
  96                         CONFIG_SYS_NOR_FTIM0,
  97                         CONFIG_SYS_NOR_FTIM1,
  98                         CONFIG_SYS_NOR_FTIM2,
  99                         CONFIG_SYS_NOR_FTIM3
 100                 },
 101         },
 102         {
 103                 "cpld",
 104                 CONFIG_SYS_CPLD_CSPR,
 105                 CONFIG_SYS_CPLD_CSPR_EXT,
 106                 CONFIG_SYS_CPLD_AMASK,
 107                 CONFIG_SYS_CPLD_CSOR,
 108                 {
 109                         CONFIG_SYS_CPLD_FTIM0,
 110                         CONFIG_SYS_CPLD_FTIM1,
 111                         CONFIG_SYS_CPLD_FTIM2,
 112                         CONFIG_SYS_CPLD_FTIM3
 113                 },
 114         }
 115 };
 116
 117 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 118 {
 119         enum boot_src src = get_boot_src();
 120
 121         if (src == BOOT_SOURCE_IFC_NAND)
 122                 regs_info->regs = ifc_cfg_nand_boot;
 123         else
 124                 regs_info->regs = ifc_cfg_nor_boot;
 125         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 126 }
 127
 128 #endif
 129 int board_early_init_f(void)
 130 {
 131         fsl_lsch2_early_init_f();
 132
 133         return 0;
 134 }
 135
 136 #ifndef CONFIG_SPL_BUILD
 137
 138 int checkboard(void)
 139 {
 140 #ifdef CONFIG_TFABOOT
 141         enum boot_src src = get_boot_src();
 142 #endif
 143         static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
 144 #ifndef CONFIG_SD_BOOT
 145         u8 cfg_rcw_src1, cfg_rcw_src2;
 146         u16 cfg_rcw_src;
 147 #endif
 148         u8 sd1refclk_sel;
 149
 150         printf("Board: LS1043ARDB, boot from ");
 151
 152 #ifdef CONFIG_TFABOOT
 153         if (src == BOOT_SOURCE_SD_MMC)
 154                 puts("SD\n");
 155         else {
 156 #endif
 157
 158 #ifdef CONFIG_SD_BOOT
 159         puts("SD\n");
 160 #else
 161         cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
 162         cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
 163         cpld_rev_bit(&cfg_rcw_src1);
 164         cfg_rcw_src = cfg_rcw_src1;
 165         cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
 166
 167         if (cfg_rcw_src == 0x25)
 168                 printf("vBank %d\n", CPLD_READ(vbank));
 169         else if (cfg_rcw_src == 0x106)
 170                 puts("NAND\n");
 171         else
 172                 printf("Invalid setting of SW4\n");
 173 #endif
 174
 175 #ifdef CONFIG_TFABOOT
 176         }
 177 #endif
 178         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
 179                CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
 180
 181         puts("SERDES Reference Clocks:\n");
 182         sd1refclk_sel = CPLD_READ(sd1refclk_sel);
 183         printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
 184
 185         return 0;
 186 }
 187
 188 int board_init(void)
 189 {
 190         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 191
 192 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 193         erratum_a010315();
 194 #endif
 195
 196 #ifdef CONFIG_FSL_IFC
 197         init_final_memctl_regs();
 198 #endif
 199
 200 #ifdef CONFIG_NXP_ESBC
 201         /* In case of Secure Boot, the IBR configures the SMMU
 202          * to allow only Secure transactions.
 203          * SMMU must be reset in bypass mode.
 204          * Set the ClientPD bit and Clear the USFCFG Bit
 205          */
 206         u32 val;
 207         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 208         out_le32(SMMU_SCR0, val);
 209         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 210         out_le32(SMMU_NSCR0, val);
 211 #endif
 212
 213 #ifdef CONFIG_FSL_CAAM
 214         sec_init();
 215 #endif
 216
 217 #ifdef CONFIG_FSL_LS_PPA
 218         ppa_init();
 219 #endif
 220
 221 #ifdef CONFIG_U_QE
 222         u_qe_init();
 223 #endif
 224         /* invert AQR105 IRQ pins polarity */
 225         out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 226
 227         return 0;
 228 }
 229
 230 int config_board_mux(void)
 231 {
 232         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 233         u32 usb_pwrfault;
 234
 235         if (hwconfig("qe-hdlc")) {
 236                 out_be32(&scfg->rcwpmuxcr0,
 237                          (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
 238                 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
 239                        in_be32(&scfg->rcwpmuxcr0));
 240         } else {
 241 #ifdef CONFIG_HAS_FSL_XHCI_USB
 242                 out_be32(&scfg->rcwpmuxcr0, 0x3333);
 243                 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 244                 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 245                                 SCFG_USBPWRFAULT_USB3_SHIFT) |
 246                                 (SCFG_USBPWRFAULT_DEDICATED <<
 247                                 SCFG_USBPWRFAULT_USB2_SHIFT) |
 248                                 (SCFG_USBPWRFAULT_SHARED <<
 249                                  SCFG_USBPWRFAULT_USB1_SHIFT);
 250                 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 251 #endif
 252         }
 253         return 0;
 254 }
 255
 256 #if defined(CONFIG_MISC_INIT_R)
 257 int misc_init_r(void)
 258 {
 259         config_board_mux();
 260         return 0;
 261 }
 262 #endif
 263
 264 void fdt_del_qe(void *blob)
 265 {
 266         int nodeoff = 0;
 267
 268         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 269                                 "fsl,qe")) >= 0) {
 270                 fdt_del_node(blob, nodeoff);
 271         }
 272 }
 273
 274 int ft_board_setup(void *blob, struct bd_info *bd)
 275 {
 276         u64 base[CONFIG_NR_DRAM_BANKS];
 277         u64 size[CONFIG_NR_DRAM_BANKS];
 278
 279         /* fixup DT for the two DDR banks */
 280         base[0] = gd->bd->bi_dram[0].start;
 281         size[0] = gd->bd->bi_dram[0].size;
 282         base[1] = gd->bd->bi_dram[1].start;
 283         size[1] = gd->bd->bi_dram[1].size;
 284
 285         fdt_fixup_memory_banks(blob, base, size, 2);
 286         ft_cpu_setup(blob, bd);
 287
 288 #ifdef CONFIG_SYS_DPAA_FMAN
 289 #ifndef CONFIG_DM_ETH
 290         fdt_fixup_fman_ethernet(blob);
 291 #endif
 292 #endif
 293
 294         fdt_fixup_icid(blob);
 295
 296         /*
 297          * qe-hdlc and usb multi-use the pins,
 298          * when set hwconfig to qe-hdlc, delete usb node.
 299          */
 300         if (hwconfig("qe-hdlc"))
 301 #ifdef CONFIG_HAS_FSL_XHCI_USB
 302                 fdt_del_node_and_alias(blob, "usb1");
 303 #endif
 304         /*
 305          * qe just support qe-uart and qe-hdlc,
 306          * if qe-uart and qe-hdlc are not set in hwconfig,
 307          * delete qe node.
 308          */
 309         if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
 310                 fdt_del_qe(blob);
 311
 312         return 0;
 313 }
 314
 315 u8 flash_read8(void *addr)
 316 {
 317         return __raw_readb(addr + 1);
 318 }
 319
 320 void flash_write16(u16 val, void *addr)
 321 {
 322         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 323
 324         __raw_writew(shftval, addr);
 325 }
 326
 327 u16 flash_read16(void *addr)
 328 {
 329         u16 val = __raw_readw(addr);
 330
 331         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 332 }
 333
 334 #endif