board/freescale/ls1043ardb/ls1043ardb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <asm/arch/soc.h>
  13 #include <fdt_support.h>
  14 #include <hwconfig.h>
  15 #include <ahci.h>
  16 #include <mmc.h>
  17 #include <scsi.h>
  18 #include <fm_eth.h>
  19 #include <fsl_csu.h>
  20 #include <fsl_esdhc.h>
  21 #include <fsl_ifc.h>
  22 #include <fsl_sec.h>
  23 #include "cpld.h"
  24 #ifdef CONFIG_U_QE
  25 #include <fsl_qe.h>
  26 #endif
  27 #ifdef CONFIG_FSL_LS_PPA
  28 #include <asm/arch/ppa.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int checkboard(void)
  34 {
  35         static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
  36 #ifndef CONFIG_SD_BOOT
  37         u8 cfg_rcw_src1, cfg_rcw_src2;
  38         u16 cfg_rcw_src;
  39 #endif
  40         u8 sd1refclk_sel;
  41
  42         printf("Board: LS1043ARDB, boot from ");
  43
  44 #ifdef CONFIG_SD_BOOT
  45         puts("SD\n");
  46 #else
  47         cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
  48         cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
  49         cpld_rev_bit(&cfg_rcw_src1);
  50         cfg_rcw_src = cfg_rcw_src1;
  51         cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
  52
  53         if (cfg_rcw_src == 0x25)
  54                 printf("vBank %d\n", CPLD_READ(vbank));
  55         else if (cfg_rcw_src == 0x106)
  56                 puts("NAND\n");
  57         else
  58                 printf("Invalid setting of SW4\n");
  59 #endif
  60
  61         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
  62                CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
  63
  64         puts("SERDES Reference Clocks:\n");
  65         sd1refclk_sel = CPLD_READ(sd1refclk_sel);
  66         printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
  67
  68         return 0;
  69 }
  70
  71 int dram_init(void)
  72 {
  73         gd->ram_size = initdram(0);
  74
  75         return 0;
  76 }
  77
  78 int board_early_init_f(void)
  79 {
  80         fsl_lsch2_early_init_f();
  81
  82         return 0;
  83 }
  84
  85 int board_init(void)
  86 {
  87         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  88
  89 #ifdef CONFIG_FSL_IFC
  90         init_final_memctl_regs();
  91 #endif
  92
  93 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  94         enable_layerscape_ns_access();
  95 #endif
  96
  97 #ifdef CONFIG_SECURE_BOOT
  98         /* In case of Secure Boot, the IBR configures the SMMU
  99          * to allow only Secure transactions.
 100          * SMMU must be reset in bypass mode.
 101          * Set the ClientPD bit and Clear the USFCFG Bit
 102          */
 103         u32 val;
 104         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 105         out_le32(SMMU_SCR0, val);
 106         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 107         out_le32(SMMU_NSCR0, val);
 108 #endif
 109
 110 #ifdef CONFIG_FSL_CAAM
 111         sec_init();
 112 #endif
 113
 114 #ifdef CONFIG_FSL_LS_PPA
 115         ppa_init();
 116 #endif
 117
 118 #ifdef CONFIG_U_QE
 119         u_qe_init();
 120 #endif
 121         /* invert AQR105 IRQ pins polarity */
 122         out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 123
 124         return 0;
 125 }
 126
 127 int config_board_mux(void)
 128 {
 129         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 130         u32 usb_pwrfault;
 131
 132         if (hwconfig("qe-hdlc")) {
 133                 out_be32(&scfg->rcwpmuxcr0,
 134                          (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
 135                 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
 136                        in_be32(&scfg->rcwpmuxcr0));
 137         } else {
 138 #ifdef CONFIG_HAS_FSL_XHCI_USB
 139                 out_be32(&scfg->rcwpmuxcr0, 0x3333);
 140                 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 141                 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 142                                 SCFG_USBPWRFAULT_USB3_SHIFT) |
 143                                 (SCFG_USBPWRFAULT_DEDICATED <<
 144                                 SCFG_USBPWRFAULT_USB2_SHIFT) |
 145                                 (SCFG_USBPWRFAULT_SHARED <<
 146                                  SCFG_USBPWRFAULT_USB1_SHIFT);
 147                 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 148 #endif
 149         }
 150         return 0;
 151 }
 152
 153 #if defined(CONFIG_MISC_INIT_R)
 154 int misc_init_r(void)
 155 {
 156         config_board_mux();
 157         return 0;
 158 }
 159 #endif
 160
 161 void fdt_del_qe(void *blob)
 162 {
 163         int nodeoff = 0;
 164
 165         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 166                                 "fsl,qe")) >= 0) {
 167                 fdt_del_node(blob, nodeoff);
 168         }
 169 }
 170
 171 int ft_board_setup(void *blob, bd_t *bd)
 172 {
 173         u64 base[CONFIG_NR_DRAM_BANKS];
 174         u64 size[CONFIG_NR_DRAM_BANKS];
 175
 176         /* fixup DT for the two DDR banks */
 177         base[0] = gd->bd->bi_dram[0].start;
 178         size[0] = gd->bd->bi_dram[0].size;
 179         base[1] = gd->bd->bi_dram[1].start;
 180         size[1] = gd->bd->bi_dram[1].size;
 181
 182         fdt_fixup_memory_banks(blob, base, size, 2);
 183         ft_cpu_setup(blob, bd);
 184
 185 #ifdef CONFIG_SYS_DPAA_FMAN
 186         fdt_fixup_fman_ethernet(blob);
 187 #endif
 188
 189         /*
 190          * qe-hdlc and usb multi-use the pins,
 191          * when set hwconfig to qe-hdlc, delete usb node.
 192          */
 193         if (hwconfig("qe-hdlc"))
 194 #ifdef CONFIG_HAS_FSL_XHCI_USB
 195                 fdt_del_node_and_alias(blob, "usb1");
 196 #endif
 197         /*
 198          * qe just support qe-uart and qe-hdlc,
 199          * if qe-uart and qe-hdlc are not set in hwconfig,
 200          * delete qe node.
 201          */
 202         if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
 203                 fdt_del_qe(blob);
 204
 205         return 0;
 206 }
 207
 208 u8 flash_read8(void *addr)
 209 {
 210         return __raw_readb(addr + 1);
 211 }
 212
 213 void flash_write16(u16 val, void *addr)
 214 {
 215         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 216
 217         __raw_writew(shftval, addr);
 218 }
 219
 220 u16 flash_read16(void *addr)
 221 {
 222         u16 val = __raw_readw(addr);
 223
 224         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 225 }