2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
17 #include <fsl_esdhc.h>
21 DECLARE_GLOBAL_DATA_PTR;
25 static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
26 u8 cfg_rcw_src1, cfg_rcw_src2;
30 printf("Board: LS1043ARDB, boot from ");
32 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
33 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
34 cpld_rev_bit(&cfg_rcw_src1);
35 cfg_rcw_src = cfg_rcw_src1;
36 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
38 if (cfg_rcw_src == 0x25)
39 printf("vBank %d\n", CPLD_READ(vbank));
40 else if (cfg_rcw_src == 0x106)
43 printf("Invalid setting of SW4\n");
45 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
46 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
48 puts("SERDES Reference Clocks:\n");
49 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
50 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
57 gd->ram_size = initdram(0);
62 int board_early_init_f(void)
64 fsl_lsch2_early_init_f();
70 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
73 * Set CCI-400 control override register to enable barrier
76 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
79 init_final_memctl_regs();
82 #ifdef CONFIG_ENV_IS_NOWHERE
83 gd->env_addr = (ulong)&default_environment[0];
86 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
87 enable_layerscape_ns_access();
93 int config_board_mux(void)
98 #if defined(CONFIG_MISC_INIT_R)
107 int ft_board_setup(void *blob, bd_t *bd)
109 ft_cpu_setup(blob, bd);
114 u8 flash_read8(void *addr)
116 return __raw_readb(addr + 1);
119 void flash_write16(u16 val, void *addr)
121 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
123 __raw_writew(shftval, addr);
126 u16 flash_read16(void *addr)
128 u16 val = __raw_readw(addr);
130 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);