2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <fdt_support.h>
19 #include <fsl_esdhc.h>
26 #ifdef CONFIG_FSL_LS_PPA
27 #include <asm/arch/ppa.h>
30 DECLARE_GLOBAL_DATA_PTR;
34 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
35 #ifndef CONFIG_SD_BOOT
36 u8 cfg_rcw_src1, cfg_rcw_src2;
41 printf("Board: LS1043ARDB, boot from ");
46 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
47 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
48 cpld_rev_bit(&cfg_rcw_src1);
49 cfg_rcw_src = cfg_rcw_src1;
50 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
52 if (cfg_rcw_src == 0x25)
53 printf("vBank %d\n", CPLD_READ(vbank));
54 else if (cfg_rcw_src == 0x106)
57 printf("Invalid setting of SW4\n");
60 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
61 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
63 puts("SERDES Reference Clocks:\n");
64 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
65 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
72 gd->ram_size = initdram(0);
77 int board_early_init_f(void)
79 fsl_lsch2_early_init_f();
86 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
89 init_final_memctl_regs();
92 #ifdef CONFIG_SECURE_BOOT
93 /* In case of Secure Boot, the IBR configures the SMMU
94 * to allow only Secure transactions.
95 * SMMU must be reset in bypass mode.
96 * Set the ClientPD bit and Clear the USFCFG Bit
99 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
100 out_le32(SMMU_SCR0, val);
101 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
102 out_le32(SMMU_NSCR0, val);
105 #ifdef CONFIG_FSL_CAAM
109 #ifdef CONFIG_FSL_LS_PPA
116 /* invert AQR105 IRQ pins polarity */
117 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
122 int config_board_mux(void)
124 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
127 if (hwconfig("qe-hdlc")) {
128 out_be32(&scfg->rcwpmuxcr0,
129 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
130 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
131 in_be32(&scfg->rcwpmuxcr0));
133 #ifdef CONFIG_HAS_FSL_XHCI_USB
134 out_be32(&scfg->rcwpmuxcr0, 0x3333);
135 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
136 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
137 SCFG_USBPWRFAULT_USB3_SHIFT) |
138 (SCFG_USBPWRFAULT_DEDICATED <<
139 SCFG_USBPWRFAULT_USB2_SHIFT) |
140 (SCFG_USBPWRFAULT_SHARED <<
141 SCFG_USBPWRFAULT_USB1_SHIFT);
142 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
148 #if defined(CONFIG_MISC_INIT_R)
149 int misc_init_r(void)
156 void fdt_del_qe(void *blob)
160 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
162 fdt_del_node(blob, nodeoff);
166 int ft_board_setup(void *blob, bd_t *bd)
168 u64 base[CONFIG_NR_DRAM_BANKS];
169 u64 size[CONFIG_NR_DRAM_BANKS];
171 /* fixup DT for the two DDR banks */
172 base[0] = gd->bd->bi_dram[0].start;
173 size[0] = gd->bd->bi_dram[0].size;
174 base[1] = gd->bd->bi_dram[1].start;
175 size[1] = gd->bd->bi_dram[1].size;
177 fdt_fixup_memory_banks(blob, base, size, 2);
178 ft_cpu_setup(blob, bd);
180 #ifdef CONFIG_SYS_DPAA_FMAN
181 fdt_fixup_fman_ethernet(blob);
185 * qe-hdlc and usb multi-use the pins,
186 * when set hwconfig to qe-hdlc, delete usb node.
188 if (hwconfig("qe-hdlc"))
189 #ifdef CONFIG_HAS_FSL_XHCI_USB
190 fdt_del_node_and_alias(blob, "usb1");
193 * qe just support qe-uart and qe-hdlc,
194 * if qe-uart and qe-hdlc are not set in hwconfig,
197 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
203 u8 flash_read8(void *addr)
205 return __raw_readb(addr + 1);
208 void flash_write16(u16 val, void *addr)
210 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
212 __raw_writew(shftval, addr);
215 u16 flash_read16(void *addr)
217 u16 val = __raw_readw(addr);
219 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);