board/freescale/ls1043ardb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <fsl_ddr_sdram.h>
   8 #include <fsl_ddr_dimm_params.h>
   9 #include "ddr.h"
  10 #include <log.h>
  11 #include <vsprintf.h>
  12 #ifdef CONFIG_FSL_DEEP_SLEEP
  13 #include <fsl_sleep.h>
  14 #endif
  15 #include <asm/arch/clock.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 void fsl_ddr_board_options(memctl_options_t *popts,
  20                            dimm_params_t *pdimm,
  21                            unsigned int ctrl_num)
  22 {
  23         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  24         ulong ddr_freq;
  25
  26         if (ctrl_num > 1) {
  27                 printf("Not supported controller number %d\n", ctrl_num);
  28                 return;
  29         }
  30         if (!pdimm->n_ranks)
  31                 return;
  32
  33         pbsp = udimms[0];
  34
  35         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  36          * freqency and n_banks specified in board_specific_parameters table.
  37          */
  38         ddr_freq = get_ddr_freq(0) / 1000000;
  39         while (pbsp->datarate_mhz_high) {
  40                 if (pbsp->n_ranks == pdimm->n_ranks) {
  41                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  42                                 popts->clk_adjust = pbsp->clk_adjust;
  43                                 popts->wrlvl_start = pbsp->wrlvl_start;
  44                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  45                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  46                                 popts->cpo_override = pbsp->cpo_override;
  47                                 popts->write_data_delay =
  48                                         pbsp->write_data_delay;
  49                                 goto found;
  50                         }
  51                         pbsp_highest = pbsp;
  52                 }
  53                 pbsp++;
  54         }
  55
  56         if (pbsp_highest) {
  57                 printf("Error: board specific timing not found for %lu MT/s\n",
  58                        ddr_freq);
  59                 printf("Trying to use the highest speed (%u) parameters\n",
  60                        pbsp_highest->datarate_mhz_high);
  61                 popts->clk_adjust = pbsp_highest->clk_adjust;
  62                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  63                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  64                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  65         } else {
  66                 panic("DIMM is not supported by this board");
  67         }
  68 found:
  69         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  70               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  71
  72         /* force DDR bus width to 32 bits */
  73         popts->data_bus_width = 1;
  74         popts->otf_burst_chop_en = 0;
  75         popts->burst_length = DDR_BL8;
  76
  77         /*
  78          * Factors to consider for half-strength driver enable:
  79          *      - number of DIMMs installed
  80          */
  81         popts->half_strength_driver_enable = 1;
  82         /*
  83          * Write leveling override
  84          */
  85         popts->wrlvl_override = 1;
  86         popts->wrlvl_sample = 0xf;
  87
  88         /*
  89          * Rtt and Rtt_WR override
  90          */
  91         popts->rtt_override = 0;
  92
  93         /* Enable ZQ calibration */
  94         popts->zq_en = 1;
  95
  96         /* optimize cpo for erratum A-009942 */
  97         popts->cpo_sample = 0x46;
  98
  99         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 100         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 101                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 102 }
 103
 104 /* DDR model number: MT40A512M8HX-093E */
 105 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 106 dimm_params_t ddr_raw_timing = {
 107         .n_ranks = 1,
 108         .rank_density = 2147483648u,
 109         .capacity = 2147483648u,
 110         .primary_sdram_width = 32,
 111         .ec_sdram_width = 0,
 112         .registered_dimm = 0,
 113         .mirrored_dimm = 0,
 114         .n_row_addr = 15,
 115         .n_col_addr = 10,
 116         .bank_addr_bits = 0,
 117         .bank_group_bits = 2,
 118         .edc_config = 0,
 119         .burst_lengths_bitmask = 0x0c,
 120
 121         .tckmin_x_ps = 938,
 122         .tckmax_ps = 1500,
 123         .caslat_x = 0x000DFA00,
 124         .taa_ps = 13500,
 125         .trcd_ps = 13500,
 126         .trp_ps = 13500,
 127         .tras_ps = 33000,
 128         .trc_ps = 46500,
 129         .trfc1_ps = 260000,
 130         .trfc2_ps = 160000,
 131         .trfc4_ps = 110000,
 132         .tfaw_ps = 21000,
 133         .trrds_ps = 3700,
 134         .trrdl_ps = 5300,
 135         .tccdl_ps = 5355,
 136         .refresh_rate_ps = 7800000,
 137         .dq_mapping[0] = 0x0,
 138         .dq_mapping[1] = 0x0,
 139         .dq_mapping[2] = 0x0,
 140         .dq_mapping[3] = 0x0,
 141         .dq_mapping[4] = 0x0,
 142         .dq_mapping[5] = 0x0,
 143         .dq_mapping[6] = 0x0,
 144         .dq_mapping[7] = 0x0,
 145         .dq_mapping[8] = 0x0,
 146         .dq_mapping[9] = 0x0,
 147         .dq_mapping[10] = 0x0,
 148         .dq_mapping[11] = 0x0,
 149         .dq_mapping[12] = 0x0,
 150         .dq_mapping[13] = 0x0,
 151         .dq_mapping[14] = 0x0,
 152         .dq_mapping[15] = 0x0,
 153         .dq_mapping[16] = 0x0,
 154         .dq_mapping[17] = 0x0,
 155         .dq_mapping_ors = 0,
 156 };
 157
 158 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 159                             unsigned int controller_number,
 160                             unsigned int dimm_number)
 161 {
 162         static const char dimm_model[] = "Fixed DDR on board";
 163
 164         if (((controller_number == 0) && (dimm_number == 0)) ||
 165             ((controller_number == 1) && (dimm_number == 0))) {
 166                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 167                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 168                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 169         }
 170
 171         return 0;
 172 }
 173 #else
 174
 175 phys_size_t fixed_sdram(void)
 176 {
 177         int i;
 178         char buf[32];
 179         fsl_ddr_cfg_regs_t ddr_cfg_regs;
 180         phys_size_t ddr_size;
 181         ulong ddr_freq, ddr_freq_mhz;
 182
 183         ddr_freq = get_ddr_freq(0);
 184         ddr_freq_mhz = ddr_freq / 1000000;
 185
 186         printf("Configuring DDR for %s MT/s data rate\n",
 187                strmhz(buf, ddr_freq));
 188
 189         for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
 190                 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
 191                     (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
 192                         memcpy(&ddr_cfg_regs,
 193                                fixed_ddr_parm_0[i].ddr_settings,
 194                                sizeof(ddr_cfg_regs));
 195                         break;
 196                 }
 197         }
 198
 199         if (fixed_ddr_parm_0[i].max_freq == 0)
 200                 panic("Unsupported DDR data rate %s MT/s data rate\n",
 201                       strmhz(buf, ddr_freq));
 202
 203         ddr_size = (phys_size_t)2048 * 1024 * 1024;
 204         fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 205
 206         return ddr_size;
 207 }
 208 #endif
 209
 210 #ifdef CONFIG_TFABOOT
 211 int fsl_initdram(void)
 212 {
 213         gd->ram_size = tfa_get_dram_size();
 214         if (!gd->ram_size)
 215 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 216                 gd->ram_size = fsl_ddr_sdram_size();
 217 #else
 218                 gd->ram_size = 0x80000000;
 219 #endif
 220                 return 0;
 221 }
 222 #else
 223 int fsl_initdram(void)
 224 {
 225         phys_size_t dram_size;
 226
 227 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 228 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
 229         puts("Initializing DDR....\n");
 230         dram_size = fsl_ddr_sdram();
 231 #else
 232         dram_size =  fsl_ddr_sdram_size();
 233 #endif
 234 #else
 235 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
 236         puts("Initialzing DDR using fixed setting\n");
 237         dram_size = fixed_sdram();
 238 #else
 239         gd->ram_size = 0x80000000;
 240
 241         return 0;
 242 #endif
 243 #endif
 244         erratum_a008850_post();
 245
 246 #ifdef CONFIG_FSL_DEEP_SLEEP
 247         fsl_dp_ddr_restore();
 248 #endif
 249
 250         gd->ram_size = dram_size;
 251
 252         return 0;
 253 }
 254 #endif