board/freescale/ls1043ardb/ddr.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ddr_sdram.h>
   9 #include <fsl_ddr_dimm_params.h>
  10 #include "ddr.h"
  11 #ifdef CONFIG_FSL_DEEP_SLEEP
  12 #include <fsl_sleep.h>
  13 #endif
  14 #include <asm/arch/clock.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 void fsl_ddr_board_options(memctl_options_t *popts,
  19                            dimm_params_t *pdimm,
  20                            unsigned int ctrl_num)
  21 {
  22         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  23         ulong ddr_freq;
  24
  25         if (ctrl_num > 1) {
  26                 printf("Not supported controller number %d\n", ctrl_num);
  27                 return;
  28         }
  29         if (!pdimm->n_ranks)
  30                 return;
  31
  32         pbsp = udimms[0];
  33
  34         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  35          * freqency and n_banks specified in board_specific_parameters table.
  36          */
  37         ddr_freq = get_ddr_freq(0) / 1000000;
  38         while (pbsp->datarate_mhz_high) {
  39                 if (pbsp->n_ranks == pdimm->n_ranks) {
  40                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  41                                 popts->clk_adjust = pbsp->clk_adjust;
  42                                 popts->wrlvl_start = pbsp->wrlvl_start;
  43                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  44                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  45                                 popts->cpo_override = pbsp->cpo_override;
  46                                 popts->write_data_delay =
  47                                         pbsp->write_data_delay;
  48                                 goto found;
  49                         }
  50                         pbsp_highest = pbsp;
  51                 }
  52                 pbsp++;
  53         }
  54
  55         if (pbsp_highest) {
  56                 printf("Error: board specific timing not found for %lu MT/s\n",
  57                        ddr_freq);
  58                 printf("Trying to use the highest speed (%u) parameters\n",
  59                        pbsp_highest->datarate_mhz_high);
  60                 popts->clk_adjust = pbsp_highest->clk_adjust;
  61                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  62                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  63                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  64         } else {
  65                 panic("DIMM is not supported by this board");
  66         }
  67 found:
  68         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  69               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  70
  71         /* force DDR bus width to 32 bits */
  72         popts->data_bus_width = 1;
  73         popts->otf_burst_chop_en = 0;
  74         popts->burst_length = DDR_BL8;
  75
  76         /*
  77          * Factors to consider for half-strength driver enable:
  78          *      - number of DIMMs installed
  79          */
  80         popts->half_strength_driver_enable = 1;
  81         /*
  82          * Write leveling override
  83          */
  84         popts->wrlvl_override = 1;
  85         popts->wrlvl_sample = 0xf;
  86
  87         /*
  88          * Rtt and Rtt_WR override
  89          */
  90         popts->rtt_override = 0;
  91
  92         /* Enable ZQ calibration */
  93         popts->zq_en = 1;
  94
  95         /* optimize cpo for erratum A-009942 */
  96         popts->cpo_sample = 0x46;
  97
  98         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  99         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 100                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 101 }
 102
 103 /* DDR model number: MT40A512M8HX-093E */
 104 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 105 dimm_params_t ddr_raw_timing = {
 106         .n_ranks = 1,
 107         .rank_density = 2147483648u,
 108         .capacity = 2147483648u,
 109         .primary_sdram_width = 32,
 110         .ec_sdram_width = 0,
 111         .registered_dimm = 0,
 112         .mirrored_dimm = 0,
 113         .n_row_addr = 15,
 114         .n_col_addr = 10,
 115         .bank_addr_bits = 0,
 116         .bank_group_bits = 2,
 117         .edc_config = 0,
 118         .burst_lengths_bitmask = 0x0c,
 119
 120         .tckmin_x_ps = 938,
 121         .tckmax_ps = 1500,
 122         .caslat_x = 0x000DFA00,
 123         .taa_ps = 13500,
 124         .trcd_ps = 13500,
 125         .trp_ps = 13500,
 126         .tras_ps = 33000,
 127         .trc_ps = 46500,
 128         .trfc1_ps = 260000,
 129         .trfc2_ps = 160000,
 130         .trfc4_ps = 110000,
 131         .tfaw_ps = 21000,
 132         .trrds_ps = 3700,
 133         .trrdl_ps = 5300,
 134         .tccdl_ps = 5355,
 135         .refresh_rate_ps = 7800000,
 136         .dq_mapping[0] = 0x0,
 137         .dq_mapping[1] = 0x0,
 138         .dq_mapping[2] = 0x0,
 139         .dq_mapping[3] = 0x0,
 140         .dq_mapping[4] = 0x0,
 141         .dq_mapping[5] = 0x0,
 142         .dq_mapping[6] = 0x0,
 143         .dq_mapping[7] = 0x0,
 144         .dq_mapping[8] = 0x0,
 145         .dq_mapping[9] = 0x0,
 146         .dq_mapping[10] = 0x0,
 147         .dq_mapping[11] = 0x0,
 148         .dq_mapping[12] = 0x0,
 149         .dq_mapping[13] = 0x0,
 150         .dq_mapping[14] = 0x0,
 151         .dq_mapping[15] = 0x0,
 152         .dq_mapping[16] = 0x0,
 153         .dq_mapping[17] = 0x0,
 154         .dq_mapping_ors = 0,
 155 };
 156
 157 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 158                             unsigned int controller_number,
 159                             unsigned int dimm_number)
 160 {
 161         static const char dimm_model[] = "Fixed DDR on board";
 162
 163         if (((controller_number == 0) && (dimm_number == 0)) ||
 164             ((controller_number == 1) && (dimm_number == 0))) {
 165                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 166                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 167                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 168         }
 169
 170         return 0;
 171 }
 172 #endif
 173
 174 int fsl_initdram(void)
 175 {
 176         phys_size_t dram_size;
 177
 178 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
 179         puts("Initializing DDR....\n");
 180         dram_size = fsl_ddr_sdram();
 181 #else
 182         dram_size =  fsl_ddr_sdram_size();
 183 #endif
 184         erratum_a008850_post();
 185
 186 #ifdef CONFIG_FSL_DEEP_SLEEP
 187         fsl_dp_ddr_restore();
 188 #endif
 189
 190         gd->ram_size = dram_size;
 191
 192         return 0;
 193 }