board/freescale/ls1043aqds/ls1043aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <fdt_support.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/ppa.h>
  14 #include <asm/arch/fdt.h>
  15 #include <asm/arch/mmu.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/soc.h>
  18 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  19 #include <ahci.h>
  20 #include <hwconfig.h>
  21 #include <mmc.h>
  22 #include <scsi.h>
  23 #include <fm_eth.h>
  24 #include <fsl_esdhc.h>
  25 #include <fsl_ifc.h>
  26 #include <spl.h>
  27
  28 #include "../common/qixis.h"
  29 #include "ls1043aqds_qixis.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 enum {
  34         MUX_TYPE_GPIO,
  35 };
  36
  37 /* LS1043AQDS serdes mux */
  38 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  39 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  40 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  41 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  42 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  43 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  44 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  45 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  46 #define CFG_UART_MUX_MASK       0x6
  47 #define CFG_UART_MUX_SHIFT      1
  48 #define CFG_LPUART_EN           0x1
  49
  50 #ifdef CONFIG_TFABOOT
  51 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  52         {
  53                 "nor0",
  54                 CONFIG_SYS_NOR0_CSPR,
  55                 CONFIG_SYS_NOR0_CSPR_EXT,
  56                 CONFIG_SYS_NOR_AMASK,
  57                 CONFIG_SYS_NOR_CSOR,
  58                 {
  59                         CONFIG_SYS_NOR_FTIM0,
  60                         CONFIG_SYS_NOR_FTIM1,
  61                         CONFIG_SYS_NOR_FTIM2,
  62                         CONFIG_SYS_NOR_FTIM3
  63                 },
  64
  65         },
  66         {
  67                 "nor1",
  68                 CONFIG_SYS_NOR1_CSPR,
  69                 CONFIG_SYS_NOR1_CSPR_EXT,
  70                 CONFIG_SYS_NOR_AMASK,
  71                 CONFIG_SYS_NOR_CSOR,
  72                 {
  73                         CONFIG_SYS_NOR_FTIM0,
  74                         CONFIG_SYS_NOR_FTIM1,
  75                         CONFIG_SYS_NOR_FTIM2,
  76                         CONFIG_SYS_NOR_FTIM3
  77                 },
  78         },
  79         {
  80                 "nand",
  81                 CONFIG_SYS_NAND_CSPR,
  82                 CONFIG_SYS_NAND_CSPR_EXT,
  83                 CONFIG_SYS_NAND_AMASK,
  84                 CONFIG_SYS_NAND_CSOR,
  85                 {
  86                         CONFIG_SYS_NAND_FTIM0,
  87                         CONFIG_SYS_NAND_FTIM1,
  88                         CONFIG_SYS_NAND_FTIM2,
  89                         CONFIG_SYS_NAND_FTIM3
  90                 },
  91         },
  92         {
  93                 "fpga",
  94                 CONFIG_SYS_FPGA_CSPR,
  95                 CONFIG_SYS_FPGA_CSPR_EXT,
  96                 CONFIG_SYS_FPGA_AMASK,
  97                 CONFIG_SYS_FPGA_CSOR,
  98                 {
  99                         CONFIG_SYS_FPGA_FTIM0,
 100                         CONFIG_SYS_FPGA_FTIM1,
 101                         CONFIG_SYS_FPGA_FTIM2,
 102                         CONFIG_SYS_FPGA_FTIM3
 103                 },
 104         }
 105 };
 106
 107 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 108         {
 109                 "nand",
 110                 CONFIG_SYS_NAND_CSPR,
 111                 CONFIG_SYS_NAND_CSPR_EXT,
 112                 CONFIG_SYS_NAND_AMASK,
 113                 CONFIG_SYS_NAND_CSOR,
 114                 {
 115                         CONFIG_SYS_NAND_FTIM0,
 116                         CONFIG_SYS_NAND_FTIM1,
 117                         CONFIG_SYS_NAND_FTIM2,
 118                         CONFIG_SYS_NAND_FTIM3
 119                 },
 120         },
 121         {
 122                 "nor0",
 123                 CONFIG_SYS_NOR0_CSPR,
 124                 CONFIG_SYS_NOR0_CSPR_EXT,
 125                 CONFIG_SYS_NOR_AMASK,
 126                 CONFIG_SYS_NOR_CSOR,
 127                 {
 128                         CONFIG_SYS_NOR_FTIM0,
 129                         CONFIG_SYS_NOR_FTIM1,
 130                         CONFIG_SYS_NOR_FTIM2,
 131                         CONFIG_SYS_NOR_FTIM3
 132                 },
 133         },
 134         {
 135                 "nor1",
 136                 CONFIG_SYS_NOR1_CSPR,
 137                 CONFIG_SYS_NOR1_CSPR_EXT,
 138                 CONFIG_SYS_NOR_AMASK,
 139                 CONFIG_SYS_NOR_CSOR,
 140                 {
 141                         CONFIG_SYS_NOR_FTIM0,
 142                         CONFIG_SYS_NOR_FTIM1,
 143                         CONFIG_SYS_NOR_FTIM2,
 144                         CONFIG_SYS_NOR_FTIM3
 145                 },
 146         },
 147         {
 148                 "fpga",
 149                 CONFIG_SYS_FPGA_CSPR,
 150                 CONFIG_SYS_FPGA_CSPR_EXT,
 151                 CONFIG_SYS_FPGA_AMASK,
 152                 CONFIG_SYS_FPGA_CSOR,
 153                 {
 154                         CONFIG_SYS_FPGA_FTIM0,
 155                         CONFIG_SYS_FPGA_FTIM1,
 156                         CONFIG_SYS_FPGA_FTIM2,
 157                         CONFIG_SYS_FPGA_FTIM3
 158                 },
 159         }
 160 };
 161
 162 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 163 {
 164         enum boot_src src = get_boot_src();
 165
 166         if (src == BOOT_SOURCE_IFC_NAND)
 167                 regs_info->regs = ifc_cfg_nand_boot;
 168         else
 169                 regs_info->regs = ifc_cfg_nor_boot;
 170         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 171 }
 172 #endif
 173
 174 int checkboard(void)
 175 {
 176 #ifdef CONFIG_TFABOOT
 177         enum boot_src src = get_boot_src();
 178 #endif
 179         char buf[64];
 180 #ifndef CONFIG_SD_BOOT
 181         u8 sw;
 182 #endif
 183
 184         puts("Board: LS1043AQDS, boot from ");
 185
 186 #ifdef CONFIG_TFABOOT
 187         if (src == BOOT_SOURCE_SD_MMC)
 188                 puts("SD\n");
 189         else {
 190 #endif
 191
 192 #ifdef CONFIG_SD_BOOT
 193         puts("SD\n");
 194 #else
 195         sw = QIXIS_READ(brdcfg[0]);
 196         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 197
 198         if (sw < 0x8)
 199                 printf("vBank: %d\n", sw);
 200         else if (sw == 0x8)
 201                 puts("PromJet\n");
 202         else if (sw == 0x9)
 203                 puts("NAND\n");
 204         else if (sw == 0xF)
 205                 printf("QSPI\n");
 206         else
 207                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 208 #endif
 209
 210 #ifdef CONFIG_TFABOOT
 211         }
 212 #endif
 213         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 214                QIXIS_READ(id), QIXIS_READ(arch));
 215
 216         printf("FPGA:  v%d (%s), build %d\n",
 217                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 218                (int)qixis_read_minor());
 219
 220         return 0;
 221 }
 222
 223 bool if_board_diff_clk(void)
 224 {
 225         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 226
 227         return diff_conf & 0x40;
 228 }
 229
 230 unsigned long get_board_sys_clk(void)
 231 {
 232         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 233
 234         switch (sysclk_conf & 0x0f) {
 235         case QIXIS_SYSCLK_64:
 236                 return 64000000;
 237         case QIXIS_SYSCLK_83:
 238                 return 83333333;
 239         case QIXIS_SYSCLK_100:
 240                 return 100000000;
 241         case QIXIS_SYSCLK_125:
 242                 return 125000000;
 243         case QIXIS_SYSCLK_133:
 244                 return 133333333;
 245         case QIXIS_SYSCLK_150:
 246                 return 150000000;
 247         case QIXIS_SYSCLK_160:
 248                 return 160000000;
 249         case QIXIS_SYSCLK_166:
 250                 return 166666666;
 251         }
 252
 253         return 66666666;
 254 }
 255
 256 unsigned long get_board_ddr_clk(void)
 257 {
 258         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 259
 260         if (if_board_diff_clk())
 261                 return get_board_sys_clk();
 262         switch ((ddrclk_conf & 0x30) >> 4) {
 263         case QIXIS_DDRCLK_100:
 264                 return 100000000;
 265         case QIXIS_DDRCLK_125:
 266                 return 125000000;
 267         case QIXIS_DDRCLK_133:
 268                 return 133333333;
 269         }
 270
 271         return 66666666;
 272 }
 273
 274 int select_i2c_ch_pca9547(u8 ch)
 275 {
 276         int ret;
 277
 278         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 279         if (ret) {
 280                 puts("PCA: failed to select proper channel\n");
 281                 return ret;
 282         }
 283
 284         return 0;
 285 }
 286
 287 int dram_init(void)
 288 {
 289         /*
 290          * When resuming from deep sleep, the I2C channel may not be
 291          * in the default channel. So, switch to the default channel
 292          * before accessing DDR SPD.
 293          */
 294         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 295         fsl_initdram();
 296 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 297         defined(CONFIG_SPL_BUILD)
 298         /* This will break-before-make MMU for DDR */
 299         update_early_mmu_table();
 300 #endif
 301
 302         return 0;
 303 }
 304
 305 int i2c_multiplexer_select_vid_channel(u8 channel)
 306 {
 307         return select_i2c_ch_pca9547(channel);
 308 }
 309
 310 void board_retimer_init(void)
 311 {
 312         u8 reg;
 313
 314         /* Retimer is connected to I2C1_CH7_CH5 */
 315         select_i2c_ch_pca9547(I2C_MUX_CH7);
 316         reg = I2C_MUX_CH5;
 317         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 318
 319         /* Access to Control/Shared register */
 320         reg = 0x0;
 321         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 322
 323         /* Read device revision and ID */
 324         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 325         debug("Retimer version id = 0x%x\n", reg);
 326
 327         /* Enable Broadcast. All writes target all channel register sets */
 328         reg = 0x0c;
 329         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 330
 331         /* Reset Channel Registers */
 332         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 333         reg |= 0x4;
 334         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 335
 336         /* Enable override divider select and Enable Override Output Mux */
 337         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 338         reg |= 0x24;
 339         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 340
 341         /* Select VCO Divider to full rate (000) */
 342         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 343         reg &= 0x8f;
 344         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 345
 346         /* Selects active PFD MUX Input as Re-timed Data (001) */
 347         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 348         reg &= 0x3f;
 349         reg |= 0x20;
 350         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 351
 352         /* Set data rate as 10.3125 Gbps */
 353         reg = 0x0;
 354         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 355         reg = 0xb2;
 356         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 357         reg = 0x90;
 358         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 359         reg = 0xb3;
 360         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 361         reg = 0xcd;
 362         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 363
 364         /* Return the default channel */
 365         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 366 }
 367
 368 int board_early_init_f(void)
 369 {
 370 #ifdef CONFIG_HAS_FSL_XHCI_USB
 371         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 372         u32 usb_pwrfault;
 373 #endif
 374 #ifdef CONFIG_LPUART
 375         u8 uart;
 376 #endif
 377
 378 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 379         i2c_early_init_f();
 380 #endif
 381         fsl_lsch2_early_init_f();
 382
 383 #ifdef CONFIG_HAS_FSL_XHCI_USB
 384         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 385         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 386         usb_pwrfault =
 387                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 388                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 389                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 390         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 391 #endif
 392
 393 #ifdef CONFIG_LPUART
 394         /* We use lpuart0 as system console */
 395         uart = QIXIS_READ(brdcfg[14]);
 396         uart &= ~CFG_UART_MUX_MASK;
 397         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 398         QIXIS_WRITE(brdcfg[14], uart);
 399 #endif
 400
 401         return 0;
 402 }
 403
 404 #ifdef CONFIG_FSL_DEEP_SLEEP
 405 /* determine if it is a warm boot */
 406 bool is_warm_boot(void)
 407 {
 408 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 409         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 410
 411         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 412                 return 1;
 413
 414         return 0;
 415 }
 416 #endif
 417
 418 int config_board_mux(int ctrl_type)
 419 {
 420         u8 reg14;
 421
 422         reg14 = QIXIS_READ(brdcfg[14]);
 423
 424         switch (ctrl_type) {
 425         case MUX_TYPE_GPIO:
 426                 reg14 = (reg14 & (~0x30)) | 0x20;
 427                 break;
 428         default:
 429                 puts("Unsupported mux interface type\n");
 430                 return -1;
 431         }
 432
 433         QIXIS_WRITE(brdcfg[14], reg14);
 434
 435         return 0;
 436 }
 437
 438 int config_serdes_mux(void)
 439 {
 440         return 0;
 441 }
 442
 443
 444 #ifdef CONFIG_MISC_INIT_R
 445 int misc_init_r(void)
 446 {
 447         if (hwconfig("gpio"))
 448                 config_board_mux(MUX_TYPE_GPIO);
 449
 450         return 0;
 451 }
 452 #endif
 453
 454 int board_init(void)
 455 {
 456 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 457         erratum_a010315();
 458 #endif
 459
 460         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 461         board_retimer_init();
 462
 463 #ifdef CONFIG_SYS_FSL_SERDES
 464         config_serdes_mux();
 465 #endif
 466
 467 #ifdef CONFIG_FSL_LS_PPA
 468         ppa_init();
 469 #endif
 470
 471         return 0;
 472 }
 473
 474 #ifdef CONFIG_OF_BOARD_SETUP
 475 int ft_board_setup(void *blob, bd_t *bd)
 476 {
 477         u64 base[CONFIG_NR_DRAM_BANKS];
 478         u64 size[CONFIG_NR_DRAM_BANKS];
 479         u8 reg;
 480
 481         /* fixup DT for the two DDR banks */
 482         base[0] = gd->bd->bi_dram[0].start;
 483         size[0] = gd->bd->bi_dram[0].size;
 484         base[1] = gd->bd->bi_dram[1].start;
 485         size[1] = gd->bd->bi_dram[1].size;
 486
 487         fdt_fixup_memory_banks(blob, base, size, 2);
 488         ft_cpu_setup(blob, bd);
 489
 490 #ifdef CONFIG_SYS_DPAA_FMAN
 491         fdt_fixup_fman_ethernet(blob);
 492         fdt_fixup_board_enet(blob);
 493 #endif
 494
 495         fdt_fixup_icid(blob);
 496
 497         reg = QIXIS_READ(brdcfg[0]);
 498         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 499
 500         /* Disable IFC if QSPI is enabled */
 501         if (reg == 0xF)
 502                 do_fixup_by_compat(blob, "fsl,ifc",
 503                                    "status", "disabled", 8 + 1, 1);
 504
 505         return 0;
 506 }
 507 #endif
 508
 509 u8 flash_read8(void *addr)
 510 {
 511         return __raw_readb(addr + 1);
 512 }
 513
 514 void flash_write16(u16 val, void *addr)
 515 {
 516         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 517
 518         __raw_writew(shftval, addr);
 519 }
 520
 521 u16 flash_read16(void *addr)
 522 {
 523         u16 val = __raw_readw(addr);
 524
 525         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 526 }
 527
 528 #ifdef CONFIG_TFABOOT
 529 void *env_sf_get_env_addr(void)
 530 {
 531         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 532 }
 533 #endif