1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Copyright 2019-2020 NXP
9 #include <fdt_support.h>
10 #include <fsl_ddr_sdram.h>
13 #include <asm/global_data.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/ppa.h>
18 #include <asm/arch/fdt.h>
19 #include <asm/arch/mmu.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/soc.h>
22 #include <asm/arch-fsl-layerscape/fsl_icid.h>
28 #include <fsl_esdhc.h>
31 #include "../common/i2c_mux.h"
33 #include "../common/qixis.h"
34 #include "ls1043aqds_qixis.h"
36 DECLARE_GLOBAL_DATA_PTR;
42 /* LS1043AQDS serdes mux */
43 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
44 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
45 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
46 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
47 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
48 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
49 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
50 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
51 #define CFG_UART_MUX_MASK 0x6
52 #define CFG_UART_MUX_SHIFT 1
53 #define CFG_LPUART_EN 0x1
55 #ifdef CONFIG_SYS_I2C_EARLY_INIT
56 void i2c_early_init_f(void);
60 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
64 CONFIG_SYS_NOR0_CSPR_EXT,
78 CONFIG_SYS_NOR1_CSPR_EXT,
91 CONFIG_SYS_NAND_CSPR_EXT,
92 CONFIG_SYS_NAND_AMASK,
95 CONFIG_SYS_NAND_FTIM0,
96 CONFIG_SYS_NAND_FTIM1,
97 CONFIG_SYS_NAND_FTIM2,
103 CONFIG_SYS_FPGA_CSPR,
104 CONFIG_SYS_FPGA_CSPR_EXT,
105 CONFIG_SYS_FPGA_AMASK,
106 CONFIG_SYS_FPGA_CSOR,
108 CONFIG_SYS_FPGA_FTIM0,
109 CONFIG_SYS_FPGA_FTIM1,
110 CONFIG_SYS_FPGA_FTIM2,
111 CONFIG_SYS_FPGA_FTIM3
116 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
119 CONFIG_SYS_NAND_CSPR,
120 CONFIG_SYS_NAND_CSPR_EXT,
121 CONFIG_SYS_NAND_AMASK,
122 CONFIG_SYS_NAND_CSOR,
124 CONFIG_SYS_NAND_FTIM0,
125 CONFIG_SYS_NAND_FTIM1,
126 CONFIG_SYS_NAND_FTIM2,
127 CONFIG_SYS_NAND_FTIM3
132 CONFIG_SYS_NOR0_CSPR,
133 CONFIG_SYS_NOR0_CSPR_EXT,
134 CONFIG_SYS_NOR_AMASK,
137 CONFIG_SYS_NOR_FTIM0,
138 CONFIG_SYS_NOR_FTIM1,
139 CONFIG_SYS_NOR_FTIM2,
145 CONFIG_SYS_NOR1_CSPR,
146 CONFIG_SYS_NOR1_CSPR_EXT,
147 CONFIG_SYS_NOR_AMASK,
150 CONFIG_SYS_NOR_FTIM0,
151 CONFIG_SYS_NOR_FTIM1,
152 CONFIG_SYS_NOR_FTIM2,
158 CONFIG_SYS_FPGA_CSPR,
159 CONFIG_SYS_FPGA_CSPR_EXT,
160 CONFIG_SYS_FPGA_AMASK,
161 CONFIG_SYS_FPGA_CSOR,
163 CONFIG_SYS_FPGA_FTIM0,
164 CONFIG_SYS_FPGA_FTIM1,
165 CONFIG_SYS_FPGA_FTIM2,
166 CONFIG_SYS_FPGA_FTIM3
171 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
173 enum boot_src src = get_boot_src();
175 if (src == BOOT_SOURCE_IFC_NAND)
176 regs_info->regs = ifc_cfg_nand_boot;
178 regs_info->regs = ifc_cfg_nor_boot;
179 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
185 #ifdef CONFIG_TFABOOT
186 enum boot_src src = get_boot_src();
189 #ifndef CONFIG_SD_BOOT
193 puts("Board: LS1043AQDS, boot from ");
195 #ifdef CONFIG_TFABOOT
196 if (src == BOOT_SOURCE_SD_MMC)
201 #ifdef CONFIG_SD_BOOT
204 sw = QIXIS_READ(brdcfg[0]);
205 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
208 printf("vBank: %d\n", sw);
216 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
219 #ifdef CONFIG_TFABOOT
222 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
223 QIXIS_READ(id), QIXIS_READ(arch));
225 printf("FPGA: v%d (%s), build %d\n",
226 (int)QIXIS_READ(scver), qixis_read_tag(buf),
227 (int)qixis_read_minor());
232 bool if_board_diff_clk(void)
234 u8 diff_conf = QIXIS_READ(brdcfg[11]);
236 return diff_conf & 0x40;
239 unsigned long get_board_sys_clk(void)
241 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
243 switch (sysclk_conf & 0x0f) {
244 case QIXIS_SYSCLK_64:
246 case QIXIS_SYSCLK_83:
248 case QIXIS_SYSCLK_100:
250 case QIXIS_SYSCLK_125:
252 case QIXIS_SYSCLK_133:
254 case QIXIS_SYSCLK_150:
256 case QIXIS_SYSCLK_160:
258 case QIXIS_SYSCLK_166:
265 unsigned long get_board_ddr_clk(void)
267 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
269 if (if_board_diff_clk())
270 return get_board_sys_clk();
271 switch ((ddrclk_conf & 0x30) >> 4) {
272 case QIXIS_DDRCLK_100:
274 case QIXIS_DDRCLK_125:
276 case QIXIS_DDRCLK_133:
286 * When resuming from deep sleep, the I2C channel may not be
287 * in the default channel. So, switch to the default channel
288 * before accessing DDR SPD.
290 * PCA9547 mount on I2C1 bus
292 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
294 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
295 defined(CONFIG_SPL_BUILD)
296 /* This will break-before-make MMU for DDR */
297 update_early_mmu_table();
303 int i2c_multiplexer_select_vid_channel(u8 channel)
305 return select_i2c_ch_pca9547(channel, 0);
308 void board_retimer_init(void)
313 /* Retimer is connected to I2C1_CH7_CH5 */
314 select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
316 #if CONFIG_IS_ENABLED(DM_I2C)
320 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
323 printf("%s: Cannot find udev for a bus %d\n", __func__,
327 dm_i2c_write(dev, 0, ®, 1);
329 /* Access to Control/Shared register */
330 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
333 printf("%s: Cannot find udev for a bus %d\n", __func__,
339 dm_i2c_write(dev, 0xff, ®, 1);
341 /* Read device revision and ID */
342 dm_i2c_read(dev, 1, ®, 1);
343 debug("Retimer version id = 0x%x\n", reg);
345 /* Enable Broadcast. All writes target all channel register sets */
347 dm_i2c_write(dev, 0xff, ®, 1);
349 /* Reset Channel Registers */
350 dm_i2c_read(dev, 0, ®, 1);
352 dm_i2c_write(dev, 0, ®, 1);
354 /* Enable override divider select and Enable Override Output Mux */
355 dm_i2c_read(dev, 9, ®, 1);
357 dm_i2c_write(dev, 9, ®, 1);
359 /* Select VCO Divider to full rate (000) */
360 dm_i2c_read(dev, 0x18, ®, 1);
362 dm_i2c_write(dev, 0x18, ®, 1);
364 /* Selects active PFD MUX Input as Re-timed Data (001) */
365 dm_i2c_read(dev, 0x1e, ®, 1);
368 dm_i2c_write(dev, 0x1e, ®, 1);
370 /* Set data rate as 10.3125 Gbps */
372 dm_i2c_write(dev, 0x60, ®, 1);
374 dm_i2c_write(dev, 0x61, ®, 1);
376 dm_i2c_write(dev, 0x62, ®, 1);
378 dm_i2c_write(dev, 0x63, ®, 1);
380 dm_i2c_write(dev, 0x64, ®, 1);
382 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
384 /* Access to Control/Shared register */
386 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
388 /* Read device revision and ID */
389 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
390 debug("Retimer version id = 0x%x\n", reg);
392 /* Enable Broadcast. All writes target all channel register sets */
394 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
396 /* Reset Channel Registers */
397 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
399 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
401 /* Enable override divider select and Enable Override Output Mux */
402 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
404 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
406 /* Select VCO Divider to full rate (000) */
407 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
409 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
411 /* Selects active PFD MUX Input as Re-timed Data (001) */
412 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
415 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
417 /* Set data rate as 10.3125 Gbps */
419 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
421 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
423 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
425 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
427 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
430 /* Return the default channel */
431 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
434 int board_early_init_f(void)
436 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
437 #ifdef CONFIG_HAS_FSL_XHCI_USB
438 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
446 * Enable secure system counter for timer
448 out_le32(cntcr, 0x1);
450 #ifdef CONFIG_SYS_I2C_EARLY_INIT
453 fsl_lsch2_early_init_f();
455 #ifdef CONFIG_HAS_FSL_XHCI_USB
456 out_be32(&scfg->rcwpmuxcr0, 0x3333);
457 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
459 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
460 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
461 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
462 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
466 /* We use lpuart0 as system console */
467 uart = QIXIS_READ(brdcfg[14]);
468 uart &= ~CFG_UART_MUX_MASK;
469 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
470 QIXIS_WRITE(brdcfg[14], uart);
476 #ifdef CONFIG_FSL_DEEP_SLEEP
477 /* determine if it is a warm boot */
478 bool is_warm_boot(void)
480 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
481 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
483 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
490 int config_board_mux(int ctrl_type)
494 reg14 = QIXIS_READ(brdcfg[14]);
498 reg14 = (reg14 & (~0x30)) | 0x20;
501 puts("Unsupported mux interface type\n");
505 QIXIS_WRITE(brdcfg[14], reg14);
510 int config_serdes_mux(void)
516 #ifdef CONFIG_MISC_INIT_R
517 int misc_init_r(void)
519 if (hwconfig("gpio"))
520 config_board_mux(MUX_TYPE_GPIO);
528 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
532 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
533 board_retimer_init();
535 #ifdef CONFIG_SYS_FSL_SERDES
539 #ifdef CONFIG_FSL_LS_PPA
546 #ifdef CONFIG_OF_BOARD_SETUP
547 int ft_board_setup(void *blob, struct bd_info *bd)
549 u64 base[CONFIG_NR_DRAM_BANKS];
550 u64 size[CONFIG_NR_DRAM_BANKS];
553 /* fixup DT for the two DDR banks */
554 base[0] = gd->bd->bi_dram[0].start;
555 size[0] = gd->bd->bi_dram[0].size;
556 base[1] = gd->bd->bi_dram[1].start;
557 size[1] = gd->bd->bi_dram[1].size;
559 fdt_fixup_memory_banks(blob, base, size, 2);
560 ft_cpu_setup(blob, bd);
562 #ifdef CONFIG_SYS_DPAA_FMAN
563 #ifndef CONFIG_DM_ETH
564 fdt_fixup_fman_ethernet(blob);
566 fdt_fixup_board_enet(blob);
569 fdt_fixup_icid(blob);
571 reg = QIXIS_READ(brdcfg[0]);
572 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
574 /* Disable IFC if QSPI is enabled */
576 do_fixup_by_compat(blob, "fsl,ifc",
577 "status", "disabled", 8 + 1, 1);
583 u8 flash_read8(void *addr)
585 return __raw_readb(addr + 1);
588 void flash_write16(u16 val, void *addr)
590 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
592 __raw_writew(shftval, addr);
595 u16 flash_read16(void *addr)
597 u16 val = __raw_readw(addr);
599 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
602 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
603 void *env_sf_get_env_addr(void)
605 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);