1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Copyright 2019-2020 NXP
8 #include <clock_legacy.h>
10 #include <fdt_support.h>
11 #include <fsl_ddr_sdram.h>
14 #include <asm/global_data.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/fsl_serdes.h>
18 #include <asm/arch/ppa.h>
19 #include <asm/arch/fdt.h>
20 #include <asm/arch/mmu.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/soc.h>
23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
29 #include <fsl_esdhc.h>
32 #include "../common/i2c_mux.h"
34 #include "../common/qixis.h"
35 #include "ls1043aqds_qixis.h"
37 DECLARE_GLOBAL_DATA_PTR;
43 /* LS1043AQDS serdes mux */
44 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
45 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
46 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
47 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
48 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
49 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
50 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
51 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
52 #define CFG_UART_MUX_MASK 0x6
53 #define CFG_UART_MUX_SHIFT 1
54 #define CFG_LPUART_EN 0x1
57 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
61 CFG_SYS_NOR0_CSPR_EXT,
75 CFG_SYS_NOR1_CSPR_EXT,
88 CFG_SYS_NAND_CSPR_EXT,
101 CFG_SYS_FPGA_CSPR_EXT,
113 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
117 CFG_SYS_NAND_CSPR_EXT,
130 CFG_SYS_NOR0_CSPR_EXT,
143 CFG_SYS_NOR1_CSPR_EXT,
156 CFG_SYS_FPGA_CSPR_EXT,
168 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
170 enum boot_src src = get_boot_src();
172 if (src == BOOT_SOURCE_IFC_NAND)
173 regs_info->regs = ifc_cfg_nand_boot;
175 regs_info->regs = ifc_cfg_nor_boot;
176 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
182 #ifdef CONFIG_TFABOOT
183 enum boot_src src = get_boot_src();
186 #ifndef CONFIG_SD_BOOT
190 puts("Board: LS1043AQDS, boot from ");
192 #ifdef CONFIG_TFABOOT
193 if (src == BOOT_SOURCE_SD_MMC)
198 #ifdef CONFIG_SD_BOOT
201 sw = QIXIS_READ(brdcfg[0]);
202 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
205 printf("vBank: %d\n", sw);
213 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
216 #ifdef CONFIG_TFABOOT
219 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
220 QIXIS_READ(id), QIXIS_READ(arch));
222 printf("FPGA: v%d (%s), build %d\n",
223 (int)QIXIS_READ(scver), qixis_read_tag(buf),
224 (int)qixis_read_minor());
229 bool if_board_diff_clk(void)
231 u8 diff_conf = QIXIS_READ(brdcfg[11]);
233 return diff_conf & 0x40;
236 unsigned long get_board_sys_clk(void)
238 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
240 switch (sysclk_conf & 0x0f) {
241 case QIXIS_SYSCLK_64:
243 case QIXIS_SYSCLK_83:
245 case QIXIS_SYSCLK_100:
247 case QIXIS_SYSCLK_125:
249 case QIXIS_SYSCLK_133:
251 case QIXIS_SYSCLK_150:
253 case QIXIS_SYSCLK_160:
255 case QIXIS_SYSCLK_166:
262 unsigned long get_board_ddr_clk(void)
264 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
266 if (if_board_diff_clk())
267 return get_board_sys_clk();
268 switch ((ddrclk_conf & 0x30) >> 4) {
269 case QIXIS_DDRCLK_100:
271 case QIXIS_DDRCLK_125:
273 case QIXIS_DDRCLK_133:
283 * When resuming from deep sleep, the I2C channel may not be
284 * in the default channel. So, switch to the default channel
285 * before accessing DDR SPD.
287 * PCA9547 mount on I2C1 bus
289 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
291 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
292 defined(CONFIG_SPL_BUILD)
293 /* This will break-before-make MMU for DDR */
294 update_early_mmu_table();
300 int i2c_multiplexer_select_vid_channel(u8 channel)
302 return select_i2c_ch_pca9547(channel, 0);
305 void board_retimer_init(void)
310 /* Retimer is connected to I2C1_CH7_CH5 */
311 select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
313 #if CONFIG_IS_ENABLED(DM_I2C)
317 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
320 printf("%s: Cannot find udev for a bus %d\n", __func__,
324 dm_i2c_write(dev, 0, ®, 1);
326 /* Access to Control/Shared register */
327 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
330 printf("%s: Cannot find udev for a bus %d\n", __func__,
336 dm_i2c_write(dev, 0xff, ®, 1);
338 /* Read device revision and ID */
339 dm_i2c_read(dev, 1, ®, 1);
340 debug("Retimer version id = 0x%x\n", reg);
342 /* Enable Broadcast. All writes target all channel register sets */
344 dm_i2c_write(dev, 0xff, ®, 1);
346 /* Reset Channel Registers */
347 dm_i2c_read(dev, 0, ®, 1);
349 dm_i2c_write(dev, 0, ®, 1);
351 /* Enable override divider select and Enable Override Output Mux */
352 dm_i2c_read(dev, 9, ®, 1);
354 dm_i2c_write(dev, 9, ®, 1);
356 /* Select VCO Divider to full rate (000) */
357 dm_i2c_read(dev, 0x18, ®, 1);
359 dm_i2c_write(dev, 0x18, ®, 1);
361 /* Selects active PFD MUX Input as Re-timed Data (001) */
362 dm_i2c_read(dev, 0x1e, ®, 1);
365 dm_i2c_write(dev, 0x1e, ®, 1);
367 /* Set data rate as 10.3125 Gbps */
369 dm_i2c_write(dev, 0x60, ®, 1);
371 dm_i2c_write(dev, 0x61, ®, 1);
373 dm_i2c_write(dev, 0x62, ®, 1);
375 dm_i2c_write(dev, 0x63, ®, 1);
377 dm_i2c_write(dev, 0x64, ®, 1);
379 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
381 /* Access to Control/Shared register */
383 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
385 /* Read device revision and ID */
386 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
387 debug("Retimer version id = 0x%x\n", reg);
389 /* Enable Broadcast. All writes target all channel register sets */
391 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
393 /* Reset Channel Registers */
394 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
396 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
398 /* Enable override divider select and Enable Override Output Mux */
399 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
401 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
403 /* Select VCO Divider to full rate (000) */
404 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
406 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
408 /* Selects active PFD MUX Input as Re-timed Data (001) */
409 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
412 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
414 /* Set data rate as 10.3125 Gbps */
416 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
418 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
420 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
422 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
424 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
427 /* Return the default channel */
428 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
431 int board_early_init_f(void)
433 u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
434 #ifdef CONFIG_HAS_FSL_XHCI_USB
435 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
443 * Enable secure system counter for timer
445 out_le32(cntcr, 0x1);
447 #if defined(CONFIG_SYS_I2C_EARLY_INIT)
450 fsl_lsch2_early_init_f();
452 #ifdef CONFIG_HAS_FSL_XHCI_USB
453 out_be32(&scfg->rcwpmuxcr0, 0x3333);
454 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
456 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
457 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
458 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
459 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
463 /* We use lpuart0 as system console */
464 uart = QIXIS_READ(brdcfg[14]);
465 uart &= ~CFG_UART_MUX_MASK;
466 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
467 QIXIS_WRITE(brdcfg[14], uart);
473 #ifdef CONFIG_FSL_DEEP_SLEEP
474 /* determine if it is a warm boot */
475 bool is_warm_boot(void)
477 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
478 struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
480 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
487 int config_board_mux(int ctrl_type)
491 reg14 = QIXIS_READ(brdcfg[14]);
495 reg14 = (reg14 & (~0x30)) | 0x20;
498 puts("Unsupported mux interface type\n");
502 QIXIS_WRITE(brdcfg[14], reg14);
507 int config_serdes_mux(void)
513 #ifdef CONFIG_MISC_INIT_R
514 int misc_init_r(void)
516 if (hwconfig("gpio"))
517 config_board_mux(MUX_TYPE_GPIO);
525 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
529 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
530 board_retimer_init();
532 #ifdef CFG_SYS_FSL_SERDES
536 #ifdef CONFIG_FSL_LS_PPA
543 #ifdef CONFIG_OF_BOARD_SETUP
544 int ft_board_setup(void *blob, struct bd_info *bd)
546 u64 base[CONFIG_NR_DRAM_BANKS];
547 u64 size[CONFIG_NR_DRAM_BANKS];
550 /* fixup DT for the two DDR banks */
551 base[0] = gd->bd->bi_dram[0].start;
552 size[0] = gd->bd->bi_dram[0].size;
553 base[1] = gd->bd->bi_dram[1].start;
554 size[1] = gd->bd->bi_dram[1].size;
556 fdt_fixup_memory_banks(blob, base, size, 2);
557 ft_cpu_setup(blob, bd);
559 #ifdef CONFIG_FMAN_ENET
560 fdt_fixup_board_enet(blob);
563 fdt_fixup_icid(blob);
565 reg = QIXIS_READ(brdcfg[0]);
566 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
568 /* Disable IFC if QSPI is enabled */
570 do_fixup_by_compat(blob, "fsl,ifc",
571 "status", "disabled", 8 + 1, 1);
577 u8 flash_read8(void *addr)
579 return __raw_readb(addr + 1);
582 void flash_write16(u16 val, void *addr)
584 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
586 __raw_writew(shftval, addr);
589 u16 flash_read16(void *addr)
591 u16 val = __raw_readw(addr);
593 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
596 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
597 void *env_sf_get_env_addr(void)
599 return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);