board/freescale/ls1043aqds/ls1043aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ppa.h>
  15 #include <asm/arch/fdt.h>
  16 #include <asm/arch/mmu.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/soc.h>
  19 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  20 #include <ahci.h>
  21 #include <hwconfig.h>
  22 #include <mmc.h>
  23 #include <scsi.h>
  24 #include <fm_eth.h>
  25 #include <fsl_esdhc.h>
  26 #include <fsl_ifc.h>
  27 #include <spl.h>
  28
  29 #include "../common/qixis.h"
  30 #include "ls1043aqds_qixis.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 enum {
  35         MUX_TYPE_GPIO,
  36 };
  37
  38 /* LS1043AQDS serdes mux */
  39 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  40 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  41 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  42 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  43 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  44 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  45 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  46 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  47 #define CFG_UART_MUX_MASK       0x6
  48 #define CFG_UART_MUX_SHIFT      1
  49 #define CFG_LPUART_EN           0x1
  50
  51 #ifdef CONFIG_TFABOOT
  52 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  53         {
  54                 "nor0",
  55                 CONFIG_SYS_NOR0_CSPR,
  56                 CONFIG_SYS_NOR0_CSPR_EXT,
  57                 CONFIG_SYS_NOR_AMASK,
  58                 CONFIG_SYS_NOR_CSOR,
  59                 {
  60                         CONFIG_SYS_NOR_FTIM0,
  61                         CONFIG_SYS_NOR_FTIM1,
  62                         CONFIG_SYS_NOR_FTIM2,
  63                         CONFIG_SYS_NOR_FTIM3
  64                 },
  65
  66         },
  67         {
  68                 "nor1",
  69                 CONFIG_SYS_NOR1_CSPR,
  70                 CONFIG_SYS_NOR1_CSPR_EXT,
  71                 CONFIG_SYS_NOR_AMASK,
  72                 CONFIG_SYS_NOR_CSOR,
  73                 {
  74                         CONFIG_SYS_NOR_FTIM0,
  75                         CONFIG_SYS_NOR_FTIM1,
  76                         CONFIG_SYS_NOR_FTIM2,
  77                         CONFIG_SYS_NOR_FTIM3
  78                 },
  79         },
  80         {
  81                 "nand",
  82                 CONFIG_SYS_NAND_CSPR,
  83                 CONFIG_SYS_NAND_CSPR_EXT,
  84                 CONFIG_SYS_NAND_AMASK,
  85                 CONFIG_SYS_NAND_CSOR,
  86                 {
  87                         CONFIG_SYS_NAND_FTIM0,
  88                         CONFIG_SYS_NAND_FTIM1,
  89                         CONFIG_SYS_NAND_FTIM2,
  90                         CONFIG_SYS_NAND_FTIM3
  91                 },
  92         },
  93         {
  94                 "fpga",
  95                 CONFIG_SYS_FPGA_CSPR,
  96                 CONFIG_SYS_FPGA_CSPR_EXT,
  97                 CONFIG_SYS_FPGA_AMASK,
  98                 CONFIG_SYS_FPGA_CSOR,
  99                 {
 100                         CONFIG_SYS_FPGA_FTIM0,
 101                         CONFIG_SYS_FPGA_FTIM1,
 102                         CONFIG_SYS_FPGA_FTIM2,
 103                         CONFIG_SYS_FPGA_FTIM3
 104                 },
 105         }
 106 };
 107
 108 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 109         {
 110                 "nand",
 111                 CONFIG_SYS_NAND_CSPR,
 112                 CONFIG_SYS_NAND_CSPR_EXT,
 113                 CONFIG_SYS_NAND_AMASK,
 114                 CONFIG_SYS_NAND_CSOR,
 115                 {
 116                         CONFIG_SYS_NAND_FTIM0,
 117                         CONFIG_SYS_NAND_FTIM1,
 118                         CONFIG_SYS_NAND_FTIM2,
 119                         CONFIG_SYS_NAND_FTIM3
 120                 },
 121         },
 122         {
 123                 "nor0",
 124                 CONFIG_SYS_NOR0_CSPR,
 125                 CONFIG_SYS_NOR0_CSPR_EXT,
 126                 CONFIG_SYS_NOR_AMASK,
 127                 CONFIG_SYS_NOR_CSOR,
 128                 {
 129                         CONFIG_SYS_NOR_FTIM0,
 130                         CONFIG_SYS_NOR_FTIM1,
 131                         CONFIG_SYS_NOR_FTIM2,
 132                         CONFIG_SYS_NOR_FTIM3
 133                 },
 134         },
 135         {
 136                 "nor1",
 137                 CONFIG_SYS_NOR1_CSPR,
 138                 CONFIG_SYS_NOR1_CSPR_EXT,
 139                 CONFIG_SYS_NOR_AMASK,
 140                 CONFIG_SYS_NOR_CSOR,
 141                 {
 142                         CONFIG_SYS_NOR_FTIM0,
 143                         CONFIG_SYS_NOR_FTIM1,
 144                         CONFIG_SYS_NOR_FTIM2,
 145                         CONFIG_SYS_NOR_FTIM3
 146                 },
 147         },
 148         {
 149                 "fpga",
 150                 CONFIG_SYS_FPGA_CSPR,
 151                 CONFIG_SYS_FPGA_CSPR_EXT,
 152                 CONFIG_SYS_FPGA_AMASK,
 153                 CONFIG_SYS_FPGA_CSOR,
 154                 {
 155                         CONFIG_SYS_FPGA_FTIM0,
 156                         CONFIG_SYS_FPGA_FTIM1,
 157                         CONFIG_SYS_FPGA_FTIM2,
 158                         CONFIG_SYS_FPGA_FTIM3
 159                 },
 160         }
 161 };
 162
 163 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 164 {
 165         enum boot_src src = get_boot_src();
 166
 167         if (src == BOOT_SOURCE_IFC_NAND)
 168                 regs_info->regs = ifc_cfg_nand_boot;
 169         else
 170                 regs_info->regs = ifc_cfg_nor_boot;
 171         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 172 }
 173 #endif
 174
 175 int checkboard(void)
 176 {
 177 #ifdef CONFIG_TFABOOT
 178         enum boot_src src = get_boot_src();
 179 #endif
 180         char buf[64];
 181 #ifndef CONFIG_SD_BOOT
 182         u8 sw;
 183 #endif
 184
 185         puts("Board: LS1043AQDS, boot from ");
 186
 187 #ifdef CONFIG_TFABOOT
 188         if (src == BOOT_SOURCE_SD_MMC)
 189                 puts("SD\n");
 190         else {
 191 #endif
 192
 193 #ifdef CONFIG_SD_BOOT
 194         puts("SD\n");
 195 #else
 196         sw = QIXIS_READ(brdcfg[0]);
 197         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 198
 199         if (sw < 0x8)
 200                 printf("vBank: %d\n", sw);
 201         else if (sw == 0x8)
 202                 puts("PromJet\n");
 203         else if (sw == 0x9)
 204                 puts("NAND\n");
 205         else if (sw == 0xF)
 206                 printf("QSPI\n");
 207         else
 208                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 209 #endif
 210
 211 #ifdef CONFIG_TFABOOT
 212         }
 213 #endif
 214         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 215                QIXIS_READ(id), QIXIS_READ(arch));
 216
 217         printf("FPGA:  v%d (%s), build %d\n",
 218                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 219                (int)qixis_read_minor());
 220
 221         return 0;
 222 }
 223
 224 bool if_board_diff_clk(void)
 225 {
 226         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 227
 228         return diff_conf & 0x40;
 229 }
 230
 231 unsigned long get_board_sys_clk(void)
 232 {
 233         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 234
 235         switch (sysclk_conf & 0x0f) {
 236         case QIXIS_SYSCLK_64:
 237                 return 64000000;
 238         case QIXIS_SYSCLK_83:
 239                 return 83333333;
 240         case QIXIS_SYSCLK_100:
 241                 return 100000000;
 242         case QIXIS_SYSCLK_125:
 243                 return 125000000;
 244         case QIXIS_SYSCLK_133:
 245                 return 133333333;
 246         case QIXIS_SYSCLK_150:
 247                 return 150000000;
 248         case QIXIS_SYSCLK_160:
 249                 return 160000000;
 250         case QIXIS_SYSCLK_166:
 251                 return 166666666;
 252         }
 253
 254         return 66666666;
 255 }
 256
 257 unsigned long get_board_ddr_clk(void)
 258 {
 259         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 260
 261         if (if_board_diff_clk())
 262                 return get_board_sys_clk();
 263         switch ((ddrclk_conf & 0x30) >> 4) {
 264         case QIXIS_DDRCLK_100:
 265                 return 100000000;
 266         case QIXIS_DDRCLK_125:
 267                 return 125000000;
 268         case QIXIS_DDRCLK_133:
 269                 return 133333333;
 270         }
 271
 272         return 66666666;
 273 }
 274
 275 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 276 {
 277         int ret;
 278
 279 #ifdef CONFIG_DM_I2C
 280         struct udevice *dev;
 281
 282         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 283                                       1, &dev);
 284         if (ret) {
 285                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 286                        bus_num);
 287                 return ret;
 288         }
 289         ret = dm_i2c_write(dev, 0, &ch, 1);
 290 #else
 291         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 292 #endif
 293         if (ret) {
 294                 puts("PCA: failed to select proper channel\n");
 295                 return ret;
 296         }
 297
 298         return 0;
 299 }
 300
 301 int dram_init(void)
 302 {
 303         /*
 304          * When resuming from deep sleep, the I2C channel may not be
 305          * in the default channel. So, switch to the default channel
 306          * before accessing DDR SPD.
 307          *
 308          * PCA9547 mount on I2C1 bus
 309          */
 310         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 311         fsl_initdram();
 312 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 313         defined(CONFIG_SPL_BUILD)
 314         /* This will break-before-make MMU for DDR */
 315         update_early_mmu_table();
 316 #endif
 317
 318         return 0;
 319 }
 320
 321 int i2c_multiplexer_select_vid_channel(u8 channel)
 322 {
 323         return select_i2c_ch_pca9547(channel, 0);
 324 }
 325
 326 void board_retimer_init(void)
 327 {
 328         u8 reg;
 329         int bus_num = 0;
 330
 331         /* Retimer is connected to I2C1_CH7_CH5 */
 332         select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
 333         reg = I2C_MUX_CH5;
 334 #ifdef CONFIG_DM_I2C
 335         struct udevice *dev;
 336         int ret;
 337
 338         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
 339                                       1, &dev);
 340         if (ret) {
 341                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 342                        bus_num);
 343                 return;
 344         }
 345         dm_i2c_write(dev, 0, &reg, 1);
 346
 347         /* Access to Control/Shared register */
 348         ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
 349                                       1, &dev);
 350         if (ret) {
 351                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 352                        bus_num);
 353                 return;
 354         }
 355
 356         reg = 0x0;
 357         dm_i2c_write(dev, 0xff, &reg, 1);
 358
 359         /* Read device revision and ID */
 360         dm_i2c_read(dev, 1, &reg, 1);
 361         debug("Retimer version id = 0x%x\n", reg);
 362
 363         /* Enable Broadcast. All writes target all channel register sets */
 364         reg = 0x0c;
 365         dm_i2c_write(dev, 0xff, &reg, 1);
 366
 367         /* Reset Channel Registers */
 368         dm_i2c_read(dev, 0, &reg, 1);
 369         reg |= 0x4;
 370         dm_i2c_write(dev, 0, &reg, 1);
 371
 372         /* Enable override divider select and Enable Override Output Mux */
 373         dm_i2c_read(dev, 9, &reg, 1);
 374         reg |= 0x24;
 375         dm_i2c_write(dev, 9, &reg, 1);
 376
 377         /* Select VCO Divider to full rate (000) */
 378         dm_i2c_read(dev, 0x18, &reg, 1);
 379         reg &= 0x8f;
 380         dm_i2c_write(dev, 0x18, &reg, 1);
 381
 382         /* Selects active PFD MUX Input as Re-timed Data (001) */
 383         dm_i2c_read(dev, 0x1e, &reg, 1);
 384         reg &= 0x3f;
 385         reg |= 0x20;
 386         dm_i2c_write(dev, 0x1e, &reg, 1);
 387
 388         /* Set data rate as 10.3125 Gbps */
 389         reg = 0x0;
 390         dm_i2c_write(dev, 0x60, &reg, 1);
 391         reg = 0xb2;
 392         dm_i2c_write(dev, 0x61, &reg, 1);
 393         reg = 0x90;
 394         dm_i2c_write(dev, 0x62, &reg, 1);
 395         reg = 0xb3;
 396         dm_i2c_write(dev, 0x63, &reg, 1);
 397         reg = 0xcd;
 398         dm_i2c_write(dev, 0x64, &reg, 1);
 399 #else
 400         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 401
 402         /* Access to Control/Shared register */
 403         reg = 0x0;
 404         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 405
 406         /* Read device revision and ID */
 407         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 408         debug("Retimer version id = 0x%x\n", reg);
 409
 410         /* Enable Broadcast. All writes target all channel register sets */
 411         reg = 0x0c;
 412         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 413
 414         /* Reset Channel Registers */
 415         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 416         reg |= 0x4;
 417         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 418
 419         /* Enable override divider select and Enable Override Output Mux */
 420         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 421         reg |= 0x24;
 422         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 423
 424         /* Select VCO Divider to full rate (000) */
 425         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 426         reg &= 0x8f;
 427         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 428
 429         /* Selects active PFD MUX Input as Re-timed Data (001) */
 430         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 431         reg &= 0x3f;
 432         reg |= 0x20;
 433         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 434
 435         /* Set data rate as 10.3125 Gbps */
 436         reg = 0x0;
 437         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 438         reg = 0xb2;
 439         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 440         reg = 0x90;
 441         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 442         reg = 0xb3;
 443         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 444         reg = 0xcd;
 445         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 446 #endif
 447
 448         /* Return the default channel */
 449         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
 450 }
 451
 452 int board_early_init_f(void)
 453 {
 454 #ifdef CONFIG_HAS_FSL_XHCI_USB
 455         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 456         u32 usb_pwrfault;
 457 #endif
 458 #ifdef CONFIG_LPUART
 459         u8 uart;
 460 #endif
 461
 462 #ifdef CONFIG_SYS_I2C
 463 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 464         i2c_early_init_f();
 465 #endif
 466 #endif
 467         fsl_lsch2_early_init_f();
 468
 469 #ifdef CONFIG_HAS_FSL_XHCI_USB
 470         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 471         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 472         usb_pwrfault =
 473                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 474                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 475                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 476         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 477 #endif
 478
 479 #ifdef CONFIG_LPUART
 480         /* We use lpuart0 as system console */
 481         uart = QIXIS_READ(brdcfg[14]);
 482         uart &= ~CFG_UART_MUX_MASK;
 483         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 484         QIXIS_WRITE(brdcfg[14], uart);
 485 #endif
 486
 487         return 0;
 488 }
 489
 490 #ifdef CONFIG_FSL_DEEP_SLEEP
 491 /* determine if it is a warm boot */
 492 bool is_warm_boot(void)
 493 {
 494 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 495         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 496
 497         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 498                 return 1;
 499
 500         return 0;
 501 }
 502 #endif
 503
 504 int config_board_mux(int ctrl_type)
 505 {
 506         u8 reg14;
 507
 508         reg14 = QIXIS_READ(brdcfg[14]);
 509
 510         switch (ctrl_type) {
 511         case MUX_TYPE_GPIO:
 512                 reg14 = (reg14 & (~0x30)) | 0x20;
 513                 break;
 514         default:
 515                 puts("Unsupported mux interface type\n");
 516                 return -1;
 517         }
 518
 519         QIXIS_WRITE(brdcfg[14], reg14);
 520
 521         return 0;
 522 }
 523
 524 int config_serdes_mux(void)
 525 {
 526         return 0;
 527 }
 528
 529
 530 #ifdef CONFIG_MISC_INIT_R
 531 int misc_init_r(void)
 532 {
 533         if (hwconfig("gpio"))
 534                 config_board_mux(MUX_TYPE_GPIO);
 535
 536         return 0;
 537 }
 538 #endif
 539
 540 int board_init(void)
 541 {
 542 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 543         erratum_a010315();
 544 #endif
 545
 546         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 547         board_retimer_init();
 548
 549 #ifdef CONFIG_SYS_FSL_SERDES
 550         config_serdes_mux();
 551 #endif
 552
 553 #ifdef CONFIG_FSL_LS_PPA
 554         ppa_init();
 555 #endif
 556
 557         return 0;
 558 }
 559
 560 #ifdef CONFIG_OF_BOARD_SETUP
 561 int ft_board_setup(void *blob, bd_t *bd)
 562 {
 563         u64 base[CONFIG_NR_DRAM_BANKS];
 564         u64 size[CONFIG_NR_DRAM_BANKS];
 565         u8 reg;
 566
 567         /* fixup DT for the two DDR banks */
 568         base[0] = gd->bd->bi_dram[0].start;
 569         size[0] = gd->bd->bi_dram[0].size;
 570         base[1] = gd->bd->bi_dram[1].start;
 571         size[1] = gd->bd->bi_dram[1].size;
 572
 573         fdt_fixup_memory_banks(blob, base, size, 2);
 574         ft_cpu_setup(blob, bd);
 575
 576 #ifdef CONFIG_SYS_DPAA_FMAN
 577         fdt_fixup_fman_ethernet(blob);
 578         fdt_fixup_board_enet(blob);
 579 #endif
 580
 581         fdt_fixup_icid(blob);
 582
 583         reg = QIXIS_READ(brdcfg[0]);
 584         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 585
 586         /* Disable IFC if QSPI is enabled */
 587         if (reg == 0xF)
 588                 do_fixup_by_compat(blob, "fsl,ifc",
 589                                    "status", "disabled", 8 + 1, 1);
 590
 591         return 0;
 592 }
 593 #endif
 594
 595 u8 flash_read8(void *addr)
 596 {
 597         return __raw_readb(addr + 1);
 598 }
 599
 600 void flash_write16(u16 val, void *addr)
 601 {
 602         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 603
 604         __raw_writew(shftval, addr);
 605 }
 606
 607 u16 flash_read16(void *addr)
 608 {
 609         u16 val = __raw_readw(addr);
 610
 611         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 612 }
 613
 614 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 615 void *env_sf_get_env_addr(void)
 616 {
 617         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 618 }
 619 #endif