board/freescale/ls1043aqds/ls1043aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/ppa.h>
  17 #include <asm/arch/fdt.h>
  18 #include <asm/arch/mmu.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/soc.h>
  21 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  22 #include <ahci.h>
  23 #include <hwconfig.h>
  24 #include <mmc.h>
  25 #include <scsi.h>
  26 #include <fm_eth.h>
  27 #include <fsl_esdhc.h>
  28 #include <fsl_ifc.h>
  29 #include <spl.h>
  30
  31 #include "../common/qixis.h"
  32 #include "ls1043aqds_qixis.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 enum {
  37         MUX_TYPE_GPIO,
  38 };
  39
  40 /* LS1043AQDS serdes mux */
  41 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  42 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  43 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  44 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  45 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  46 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  47 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  48 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  49 #define CFG_UART_MUX_MASK       0x6
  50 #define CFG_UART_MUX_SHIFT      1
  51 #define CFG_LPUART_EN           0x1
  52
  53 #ifdef CONFIG_SYS_I2C_EARLY_INIT
  54 void i2c_early_init_f(void);
  55 #endif
  56
  57 #ifdef CONFIG_TFABOOT
  58 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  59         {
  60                 "nor0",
  61                 CONFIG_SYS_NOR0_CSPR,
  62                 CONFIG_SYS_NOR0_CSPR_EXT,
  63                 CONFIG_SYS_NOR_AMASK,
  64                 CONFIG_SYS_NOR_CSOR,
  65                 {
  66                         CONFIG_SYS_NOR_FTIM0,
  67                         CONFIG_SYS_NOR_FTIM1,
  68                         CONFIG_SYS_NOR_FTIM2,
  69                         CONFIG_SYS_NOR_FTIM3
  70                 },
  71
  72         },
  73         {
  74                 "nor1",
  75                 CONFIG_SYS_NOR1_CSPR,
  76                 CONFIG_SYS_NOR1_CSPR_EXT,
  77                 CONFIG_SYS_NOR_AMASK,
  78                 CONFIG_SYS_NOR_CSOR,
  79                 {
  80                         CONFIG_SYS_NOR_FTIM0,
  81                         CONFIG_SYS_NOR_FTIM1,
  82                         CONFIG_SYS_NOR_FTIM2,
  83                         CONFIG_SYS_NOR_FTIM3
  84                 },
  85         },
  86         {
  87                 "nand",
  88                 CONFIG_SYS_NAND_CSPR,
  89                 CONFIG_SYS_NAND_CSPR_EXT,
  90                 CONFIG_SYS_NAND_AMASK,
  91                 CONFIG_SYS_NAND_CSOR,
  92                 {
  93                         CONFIG_SYS_NAND_FTIM0,
  94                         CONFIG_SYS_NAND_FTIM1,
  95                         CONFIG_SYS_NAND_FTIM2,
  96                         CONFIG_SYS_NAND_FTIM3
  97                 },
  98         },
  99         {
 100                 "fpga",
 101                 CONFIG_SYS_FPGA_CSPR,
 102                 CONFIG_SYS_FPGA_CSPR_EXT,
 103                 CONFIG_SYS_FPGA_AMASK,
 104                 CONFIG_SYS_FPGA_CSOR,
 105                 {
 106                         CONFIG_SYS_FPGA_FTIM0,
 107                         CONFIG_SYS_FPGA_FTIM1,
 108                         CONFIG_SYS_FPGA_FTIM2,
 109                         CONFIG_SYS_FPGA_FTIM3
 110                 },
 111         }
 112 };
 113
 114 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 115         {
 116                 "nand",
 117                 CONFIG_SYS_NAND_CSPR,
 118                 CONFIG_SYS_NAND_CSPR_EXT,
 119                 CONFIG_SYS_NAND_AMASK,
 120                 CONFIG_SYS_NAND_CSOR,
 121                 {
 122                         CONFIG_SYS_NAND_FTIM0,
 123                         CONFIG_SYS_NAND_FTIM1,
 124                         CONFIG_SYS_NAND_FTIM2,
 125                         CONFIG_SYS_NAND_FTIM3
 126                 },
 127         },
 128         {
 129                 "nor0",
 130                 CONFIG_SYS_NOR0_CSPR,
 131                 CONFIG_SYS_NOR0_CSPR_EXT,
 132                 CONFIG_SYS_NOR_AMASK,
 133                 CONFIG_SYS_NOR_CSOR,
 134                 {
 135                         CONFIG_SYS_NOR_FTIM0,
 136                         CONFIG_SYS_NOR_FTIM1,
 137                         CONFIG_SYS_NOR_FTIM2,
 138                         CONFIG_SYS_NOR_FTIM3
 139                 },
 140         },
 141         {
 142                 "nor1",
 143                 CONFIG_SYS_NOR1_CSPR,
 144                 CONFIG_SYS_NOR1_CSPR_EXT,
 145                 CONFIG_SYS_NOR_AMASK,
 146                 CONFIG_SYS_NOR_CSOR,
 147                 {
 148                         CONFIG_SYS_NOR_FTIM0,
 149                         CONFIG_SYS_NOR_FTIM1,
 150                         CONFIG_SYS_NOR_FTIM2,
 151                         CONFIG_SYS_NOR_FTIM3
 152                 },
 153         },
 154         {
 155                 "fpga",
 156                 CONFIG_SYS_FPGA_CSPR,
 157                 CONFIG_SYS_FPGA_CSPR_EXT,
 158                 CONFIG_SYS_FPGA_AMASK,
 159                 CONFIG_SYS_FPGA_CSOR,
 160                 {
 161                         CONFIG_SYS_FPGA_FTIM0,
 162                         CONFIG_SYS_FPGA_FTIM1,
 163                         CONFIG_SYS_FPGA_FTIM2,
 164                         CONFIG_SYS_FPGA_FTIM3
 165                 },
 166         }
 167 };
 168
 169 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 170 {
 171         enum boot_src src = get_boot_src();
 172
 173         if (src == BOOT_SOURCE_IFC_NAND)
 174                 regs_info->regs = ifc_cfg_nand_boot;
 175         else
 176                 regs_info->regs = ifc_cfg_nor_boot;
 177         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 178 }
 179 #endif
 180
 181 int checkboard(void)
 182 {
 183 #ifdef CONFIG_TFABOOT
 184         enum boot_src src = get_boot_src();
 185 #endif
 186         char buf[64];
 187 #ifndef CONFIG_SD_BOOT
 188         u8 sw;
 189 #endif
 190
 191         puts("Board: LS1043AQDS, boot from ");
 192
 193 #ifdef CONFIG_TFABOOT
 194         if (src == BOOT_SOURCE_SD_MMC)
 195                 puts("SD\n");
 196         else {
 197 #endif
 198
 199 #ifdef CONFIG_SD_BOOT
 200         puts("SD\n");
 201 #else
 202         sw = QIXIS_READ(brdcfg[0]);
 203         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 204
 205         if (sw < 0x8)
 206                 printf("vBank: %d\n", sw);
 207         else if (sw == 0x8)
 208                 puts("PromJet\n");
 209         else if (sw == 0x9)
 210                 puts("NAND\n");
 211         else if (sw == 0xF)
 212                 printf("QSPI\n");
 213         else
 214                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 215 #endif
 216
 217 #ifdef CONFIG_TFABOOT
 218         }
 219 #endif
 220         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 221                QIXIS_READ(id), QIXIS_READ(arch));
 222
 223         printf("FPGA:  v%d (%s), build %d\n",
 224                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 225                (int)qixis_read_minor());
 226
 227         return 0;
 228 }
 229
 230 bool if_board_diff_clk(void)
 231 {
 232         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 233
 234         return diff_conf & 0x40;
 235 }
 236
 237 unsigned long get_board_sys_clk(void)
 238 {
 239         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 240
 241         switch (sysclk_conf & 0x0f) {
 242         case QIXIS_SYSCLK_64:
 243                 return 64000000;
 244         case QIXIS_SYSCLK_83:
 245                 return 83333333;
 246         case QIXIS_SYSCLK_100:
 247                 return 100000000;
 248         case QIXIS_SYSCLK_125:
 249                 return 125000000;
 250         case QIXIS_SYSCLK_133:
 251                 return 133333333;
 252         case QIXIS_SYSCLK_150:
 253                 return 150000000;
 254         case QIXIS_SYSCLK_160:
 255                 return 160000000;
 256         case QIXIS_SYSCLK_166:
 257                 return 166666666;
 258         }
 259
 260         return 66666666;
 261 }
 262
 263 unsigned long get_board_ddr_clk(void)
 264 {
 265         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 266
 267         if (if_board_diff_clk())
 268                 return get_board_sys_clk();
 269         switch ((ddrclk_conf & 0x30) >> 4) {
 270         case QIXIS_DDRCLK_100:
 271                 return 100000000;
 272         case QIXIS_DDRCLK_125:
 273                 return 125000000;
 274         case QIXIS_DDRCLK_133:
 275                 return 133333333;
 276         }
 277
 278         return 66666666;
 279 }
 280
 281 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 282 {
 283         int ret;
 284
 285 #ifdef CONFIG_DM_I2C
 286         struct udevice *dev;
 287
 288         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 289                                       1, &dev);
 290         if (ret) {
 291                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 292                        bus_num);
 293                 return ret;
 294         }
 295         ret = dm_i2c_write(dev, 0, &ch, 1);
 296 #else
 297         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 298 #endif
 299         if (ret) {
 300                 puts("PCA: failed to select proper channel\n");
 301                 return ret;
 302         }
 303
 304         return 0;
 305 }
 306
 307 int dram_init(void)
 308 {
 309         /*
 310          * When resuming from deep sleep, the I2C channel may not be
 311          * in the default channel. So, switch to the default channel
 312          * before accessing DDR SPD.
 313          *
 314          * PCA9547 mount on I2C1 bus
 315          */
 316         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 317         fsl_initdram();
 318 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 319         defined(CONFIG_SPL_BUILD)
 320         /* This will break-before-make MMU for DDR */
 321         update_early_mmu_table();
 322 #endif
 323
 324         return 0;
 325 }
 326
 327 int i2c_multiplexer_select_vid_channel(u8 channel)
 328 {
 329         return select_i2c_ch_pca9547(channel, 0);
 330 }
 331
 332 void board_retimer_init(void)
 333 {
 334         u8 reg;
 335         int bus_num = 0;
 336
 337         /* Retimer is connected to I2C1_CH7_CH5 */
 338         select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
 339         reg = I2C_MUX_CH5;
 340 #ifdef CONFIG_DM_I2C
 341         struct udevice *dev;
 342         int ret;
 343
 344         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
 345                                       1, &dev);
 346         if (ret) {
 347                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 348                        bus_num);
 349                 return;
 350         }
 351         dm_i2c_write(dev, 0, &reg, 1);
 352
 353         /* Access to Control/Shared register */
 354         ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
 355                                       1, &dev);
 356         if (ret) {
 357                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 358                        bus_num);
 359                 return;
 360         }
 361
 362         reg = 0x0;
 363         dm_i2c_write(dev, 0xff, &reg, 1);
 364
 365         /* Read device revision and ID */
 366         dm_i2c_read(dev, 1, &reg, 1);
 367         debug("Retimer version id = 0x%x\n", reg);
 368
 369         /* Enable Broadcast. All writes target all channel register sets */
 370         reg = 0x0c;
 371         dm_i2c_write(dev, 0xff, &reg, 1);
 372
 373         /* Reset Channel Registers */
 374         dm_i2c_read(dev, 0, &reg, 1);
 375         reg |= 0x4;
 376         dm_i2c_write(dev, 0, &reg, 1);
 377
 378         /* Enable override divider select and Enable Override Output Mux */
 379         dm_i2c_read(dev, 9, &reg, 1);
 380         reg |= 0x24;
 381         dm_i2c_write(dev, 9, &reg, 1);
 382
 383         /* Select VCO Divider to full rate (000) */
 384         dm_i2c_read(dev, 0x18, &reg, 1);
 385         reg &= 0x8f;
 386         dm_i2c_write(dev, 0x18, &reg, 1);
 387
 388         /* Selects active PFD MUX Input as Re-timed Data (001) */
 389         dm_i2c_read(dev, 0x1e, &reg, 1);
 390         reg &= 0x3f;
 391         reg |= 0x20;
 392         dm_i2c_write(dev, 0x1e, &reg, 1);
 393
 394         /* Set data rate as 10.3125 Gbps */
 395         reg = 0x0;
 396         dm_i2c_write(dev, 0x60, &reg, 1);
 397         reg = 0xb2;
 398         dm_i2c_write(dev, 0x61, &reg, 1);
 399         reg = 0x90;
 400         dm_i2c_write(dev, 0x62, &reg, 1);
 401         reg = 0xb3;
 402         dm_i2c_write(dev, 0x63, &reg, 1);
 403         reg = 0xcd;
 404         dm_i2c_write(dev, 0x64, &reg, 1);
 405 #else
 406         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 407
 408         /* Access to Control/Shared register */
 409         reg = 0x0;
 410         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 411
 412         /* Read device revision and ID */
 413         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 414         debug("Retimer version id = 0x%x\n", reg);
 415
 416         /* Enable Broadcast. All writes target all channel register sets */
 417         reg = 0x0c;
 418         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 419
 420         /* Reset Channel Registers */
 421         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 422         reg |= 0x4;
 423         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 424
 425         /* Enable override divider select and Enable Override Output Mux */
 426         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 427         reg |= 0x24;
 428         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 429
 430         /* Select VCO Divider to full rate (000) */
 431         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 432         reg &= 0x8f;
 433         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 434
 435         /* Selects active PFD MUX Input as Re-timed Data (001) */
 436         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 437         reg &= 0x3f;
 438         reg |= 0x20;
 439         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 440
 441         /* Set data rate as 10.3125 Gbps */
 442         reg = 0x0;
 443         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 444         reg = 0xb2;
 445         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 446         reg = 0x90;
 447         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 448         reg = 0xb3;
 449         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 450         reg = 0xcd;
 451         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 452 #endif
 453
 454         /* Return the default channel */
 455         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
 456 }
 457
 458 int board_early_init_f(void)
 459 {
 460         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 461 #ifdef CONFIG_HAS_FSL_XHCI_USB
 462         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 463         u32 usb_pwrfault;
 464 #endif
 465 #ifdef CONFIG_LPUART
 466         u8 uart;
 467 #endif
 468
 469         /*
 470          * Enable secure system counter for timer
 471          */
 472         out_le32(cntcr, 0x1);
 473
 474 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 475         i2c_early_init_f();
 476 #endif
 477         fsl_lsch2_early_init_f();
 478
 479 #ifdef CONFIG_HAS_FSL_XHCI_USB
 480         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 481         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 482         usb_pwrfault =
 483                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 484                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 485                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 486         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 487 #endif
 488
 489 #ifdef CONFIG_LPUART
 490         /* We use lpuart0 as system console */
 491         uart = QIXIS_READ(brdcfg[14]);
 492         uart &= ~CFG_UART_MUX_MASK;
 493         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 494         QIXIS_WRITE(brdcfg[14], uart);
 495 #endif
 496
 497         return 0;
 498 }
 499
 500 #ifdef CONFIG_FSL_DEEP_SLEEP
 501 /* determine if it is a warm boot */
 502 bool is_warm_boot(void)
 503 {
 504 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 505         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 506
 507         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 508                 return 1;
 509
 510         return 0;
 511 }
 512 #endif
 513
 514 int config_board_mux(int ctrl_type)
 515 {
 516         u8 reg14;
 517
 518         reg14 = QIXIS_READ(brdcfg[14]);
 519
 520         switch (ctrl_type) {
 521         case MUX_TYPE_GPIO:
 522                 reg14 = (reg14 & (~0x30)) | 0x20;
 523                 break;
 524         default:
 525                 puts("Unsupported mux interface type\n");
 526                 return -1;
 527         }
 528
 529         QIXIS_WRITE(brdcfg[14], reg14);
 530
 531         return 0;
 532 }
 533
 534 int config_serdes_mux(void)
 535 {
 536         return 0;
 537 }
 538
 539
 540 #ifdef CONFIG_MISC_INIT_R
 541 int misc_init_r(void)
 542 {
 543         if (hwconfig("gpio"))
 544                 config_board_mux(MUX_TYPE_GPIO);
 545
 546         return 0;
 547 }
 548 #endif
 549
 550 int board_init(void)
 551 {
 552 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 553         erratum_a010315();
 554 #endif
 555
 556         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 557         board_retimer_init();
 558
 559 #ifdef CONFIG_SYS_FSL_SERDES
 560         config_serdes_mux();
 561 #endif
 562
 563 #ifdef CONFIG_FSL_LS_PPA
 564         ppa_init();
 565 #endif
 566
 567         return 0;
 568 }
 569
 570 #ifdef CONFIG_OF_BOARD_SETUP
 571 int ft_board_setup(void *blob, struct bd_info *bd)
 572 {
 573         u64 base[CONFIG_NR_DRAM_BANKS];
 574         u64 size[CONFIG_NR_DRAM_BANKS];
 575         u8 reg;
 576
 577         /* fixup DT for the two DDR banks */
 578         base[0] = gd->bd->bi_dram[0].start;
 579         size[0] = gd->bd->bi_dram[0].size;
 580         base[1] = gd->bd->bi_dram[1].start;
 581         size[1] = gd->bd->bi_dram[1].size;
 582
 583         fdt_fixup_memory_banks(blob, base, size, 2);
 584         ft_cpu_setup(blob, bd);
 585
 586 #ifdef CONFIG_SYS_DPAA_FMAN
 587 #ifndef CONFIG_DM_ETH
 588         fdt_fixup_fman_ethernet(blob);
 589 #endif
 590         fdt_fixup_board_enet(blob);
 591 #endif
 592
 593         fdt_fixup_icid(blob);
 594
 595         reg = QIXIS_READ(brdcfg[0]);
 596         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 597
 598         /* Disable IFC if QSPI is enabled */
 599         if (reg == 0xF)
 600                 do_fixup_by_compat(blob, "fsl,ifc",
 601                                    "status", "disabled", 8 + 1, 1);
 602
 603         return 0;
 604 }
 605 #endif
 606
 607 u8 flash_read8(void *addr)
 608 {
 609         return __raw_readb(addr + 1);
 610 }
 611
 612 void flash_write16(u16 val, void *addr)
 613 {
 614         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 615
 616         __raw_writew(shftval, addr);
 617 }
 618
 619 u16 flash_read16(void *addr)
 620 {
 621         u16 val = __raw_readw(addr);
 622
 623         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 624 }
 625
 626 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 627 void *env_sf_get_env_addr(void)
 628 {
 629         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 630 }
 631 #endif