board/freescale/ls1043aqds/ls1043aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/fsl_serdes.h>
  15 #include <asm/arch/ppa.h>
  16 #include <asm/arch/fdt.h>
  17 #include <asm/arch/mmu.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/soc.h>
  20 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  21 #include <ahci.h>
  22 #include <hwconfig.h>
  23 #include <mmc.h>
  24 #include <scsi.h>
  25 #include <fm_eth.h>
  26 #include <fsl_esdhc.h>
  27 #include <fsl_ifc.h>
  28 #include <spl.h>
  29
  30 #include "../common/qixis.h"
  31 #include "ls1043aqds_qixis.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 enum {
  36         MUX_TYPE_GPIO,
  37 };
  38
  39 /* LS1043AQDS serdes mux */
  40 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  41 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  42 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  43 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  44 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  45 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  46 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  47 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  48 #define CFG_UART_MUX_MASK       0x6
  49 #define CFG_UART_MUX_SHIFT      1
  50 #define CFG_LPUART_EN           0x1
  51
  52 #ifdef CONFIG_TFABOOT
  53 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  54         {
  55                 "nor0",
  56                 CONFIG_SYS_NOR0_CSPR,
  57                 CONFIG_SYS_NOR0_CSPR_EXT,
  58                 CONFIG_SYS_NOR_AMASK,
  59                 CONFIG_SYS_NOR_CSOR,
  60                 {
  61                         CONFIG_SYS_NOR_FTIM0,
  62                         CONFIG_SYS_NOR_FTIM1,
  63                         CONFIG_SYS_NOR_FTIM2,
  64                         CONFIG_SYS_NOR_FTIM3
  65                 },
  66
  67         },
  68         {
  69                 "nor1",
  70                 CONFIG_SYS_NOR1_CSPR,
  71                 CONFIG_SYS_NOR1_CSPR_EXT,
  72                 CONFIG_SYS_NOR_AMASK,
  73                 CONFIG_SYS_NOR_CSOR,
  74                 {
  75                         CONFIG_SYS_NOR_FTIM0,
  76                         CONFIG_SYS_NOR_FTIM1,
  77                         CONFIG_SYS_NOR_FTIM2,
  78                         CONFIG_SYS_NOR_FTIM3
  79                 },
  80         },
  81         {
  82                 "nand",
  83                 CONFIG_SYS_NAND_CSPR,
  84                 CONFIG_SYS_NAND_CSPR_EXT,
  85                 CONFIG_SYS_NAND_AMASK,
  86                 CONFIG_SYS_NAND_CSOR,
  87                 {
  88                         CONFIG_SYS_NAND_FTIM0,
  89                         CONFIG_SYS_NAND_FTIM1,
  90                         CONFIG_SYS_NAND_FTIM2,
  91                         CONFIG_SYS_NAND_FTIM3
  92                 },
  93         },
  94         {
  95                 "fpga",
  96                 CONFIG_SYS_FPGA_CSPR,
  97                 CONFIG_SYS_FPGA_CSPR_EXT,
  98                 CONFIG_SYS_FPGA_AMASK,
  99                 CONFIG_SYS_FPGA_CSOR,
 100                 {
 101                         CONFIG_SYS_FPGA_FTIM0,
 102                         CONFIG_SYS_FPGA_FTIM1,
 103                         CONFIG_SYS_FPGA_FTIM2,
 104                         CONFIG_SYS_FPGA_FTIM3
 105                 },
 106         }
 107 };
 108
 109 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 110         {
 111                 "nand",
 112                 CONFIG_SYS_NAND_CSPR,
 113                 CONFIG_SYS_NAND_CSPR_EXT,
 114                 CONFIG_SYS_NAND_AMASK,
 115                 CONFIG_SYS_NAND_CSOR,
 116                 {
 117                         CONFIG_SYS_NAND_FTIM0,
 118                         CONFIG_SYS_NAND_FTIM1,
 119                         CONFIG_SYS_NAND_FTIM2,
 120                         CONFIG_SYS_NAND_FTIM3
 121                 },
 122         },
 123         {
 124                 "nor0",
 125                 CONFIG_SYS_NOR0_CSPR,
 126                 CONFIG_SYS_NOR0_CSPR_EXT,
 127                 CONFIG_SYS_NOR_AMASK,
 128                 CONFIG_SYS_NOR_CSOR,
 129                 {
 130                         CONFIG_SYS_NOR_FTIM0,
 131                         CONFIG_SYS_NOR_FTIM1,
 132                         CONFIG_SYS_NOR_FTIM2,
 133                         CONFIG_SYS_NOR_FTIM3
 134                 },
 135         },
 136         {
 137                 "nor1",
 138                 CONFIG_SYS_NOR1_CSPR,
 139                 CONFIG_SYS_NOR1_CSPR_EXT,
 140                 CONFIG_SYS_NOR_AMASK,
 141                 CONFIG_SYS_NOR_CSOR,
 142                 {
 143                         CONFIG_SYS_NOR_FTIM0,
 144                         CONFIG_SYS_NOR_FTIM1,
 145                         CONFIG_SYS_NOR_FTIM2,
 146                         CONFIG_SYS_NOR_FTIM3
 147                 },
 148         },
 149         {
 150                 "fpga",
 151                 CONFIG_SYS_FPGA_CSPR,
 152                 CONFIG_SYS_FPGA_CSPR_EXT,
 153                 CONFIG_SYS_FPGA_AMASK,
 154                 CONFIG_SYS_FPGA_CSOR,
 155                 {
 156                         CONFIG_SYS_FPGA_FTIM0,
 157                         CONFIG_SYS_FPGA_FTIM1,
 158                         CONFIG_SYS_FPGA_FTIM2,
 159                         CONFIG_SYS_FPGA_FTIM3
 160                 },
 161         }
 162 };
 163
 164 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 165 {
 166         enum boot_src src = get_boot_src();
 167
 168         if (src == BOOT_SOURCE_IFC_NAND)
 169                 regs_info->regs = ifc_cfg_nand_boot;
 170         else
 171                 regs_info->regs = ifc_cfg_nor_boot;
 172         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 173 }
 174 #endif
 175
 176 int checkboard(void)
 177 {
 178 #ifdef CONFIG_TFABOOT
 179         enum boot_src src = get_boot_src();
 180 #endif
 181         char buf[64];
 182 #ifndef CONFIG_SD_BOOT
 183         u8 sw;
 184 #endif
 185
 186         puts("Board: LS1043AQDS, boot from ");
 187
 188 #ifdef CONFIG_TFABOOT
 189         if (src == BOOT_SOURCE_SD_MMC)
 190                 puts("SD\n");
 191         else {
 192 #endif
 193
 194 #ifdef CONFIG_SD_BOOT
 195         puts("SD\n");
 196 #else
 197         sw = QIXIS_READ(brdcfg[0]);
 198         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 199
 200         if (sw < 0x8)
 201                 printf("vBank: %d\n", sw);
 202         else if (sw == 0x8)
 203                 puts("PromJet\n");
 204         else if (sw == 0x9)
 205                 puts("NAND\n");
 206         else if (sw == 0xF)
 207                 printf("QSPI\n");
 208         else
 209                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 210 #endif
 211
 212 #ifdef CONFIG_TFABOOT
 213         }
 214 #endif
 215         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 216                QIXIS_READ(id), QIXIS_READ(arch));
 217
 218         printf("FPGA:  v%d (%s), build %d\n",
 219                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 220                (int)qixis_read_minor());
 221
 222         return 0;
 223 }
 224
 225 bool if_board_diff_clk(void)
 226 {
 227         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 228
 229         return diff_conf & 0x40;
 230 }
 231
 232 unsigned long get_board_sys_clk(void)
 233 {
 234         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 235
 236         switch (sysclk_conf & 0x0f) {
 237         case QIXIS_SYSCLK_64:
 238                 return 64000000;
 239         case QIXIS_SYSCLK_83:
 240                 return 83333333;
 241         case QIXIS_SYSCLK_100:
 242                 return 100000000;
 243         case QIXIS_SYSCLK_125:
 244                 return 125000000;
 245         case QIXIS_SYSCLK_133:
 246                 return 133333333;
 247         case QIXIS_SYSCLK_150:
 248                 return 150000000;
 249         case QIXIS_SYSCLK_160:
 250                 return 160000000;
 251         case QIXIS_SYSCLK_166:
 252                 return 166666666;
 253         }
 254
 255         return 66666666;
 256 }
 257
 258 unsigned long get_board_ddr_clk(void)
 259 {
 260         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 261
 262         if (if_board_diff_clk())
 263                 return get_board_sys_clk();
 264         switch ((ddrclk_conf & 0x30) >> 4) {
 265         case QIXIS_DDRCLK_100:
 266                 return 100000000;
 267         case QIXIS_DDRCLK_125:
 268                 return 125000000;
 269         case QIXIS_DDRCLK_133:
 270                 return 133333333;
 271         }
 272
 273         return 66666666;
 274 }
 275
 276 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 277 {
 278         int ret;
 279
 280 #ifdef CONFIG_DM_I2C
 281         struct udevice *dev;
 282
 283         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 284                                       1, &dev);
 285         if (ret) {
 286                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 287                        bus_num);
 288                 return ret;
 289         }
 290         ret = dm_i2c_write(dev, 0, &ch, 1);
 291 #else
 292         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 293 #endif
 294         if (ret) {
 295                 puts("PCA: failed to select proper channel\n");
 296                 return ret;
 297         }
 298
 299         return 0;
 300 }
 301
 302 int dram_init(void)
 303 {
 304         /*
 305          * When resuming from deep sleep, the I2C channel may not be
 306          * in the default channel. So, switch to the default channel
 307          * before accessing DDR SPD.
 308          *
 309          * PCA9547 mount on I2C1 bus
 310          */
 311         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 312         fsl_initdram();
 313 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 314         defined(CONFIG_SPL_BUILD)
 315         /* This will break-before-make MMU for DDR */
 316         update_early_mmu_table();
 317 #endif
 318
 319         return 0;
 320 }
 321
 322 int i2c_multiplexer_select_vid_channel(u8 channel)
 323 {
 324         return select_i2c_ch_pca9547(channel, 0);
 325 }
 326
 327 void board_retimer_init(void)
 328 {
 329         u8 reg;
 330         int bus_num = 0;
 331
 332         /* Retimer is connected to I2C1_CH7_CH5 */
 333         select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
 334         reg = I2C_MUX_CH5;
 335 #ifdef CONFIG_DM_I2C
 336         struct udevice *dev;
 337         int ret;
 338
 339         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
 340                                       1, &dev);
 341         if (ret) {
 342                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 343                        bus_num);
 344                 return;
 345         }
 346         dm_i2c_write(dev, 0, &reg, 1);
 347
 348         /* Access to Control/Shared register */
 349         ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
 350                                       1, &dev);
 351         if (ret) {
 352                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 353                        bus_num);
 354                 return;
 355         }
 356
 357         reg = 0x0;
 358         dm_i2c_write(dev, 0xff, &reg, 1);
 359
 360         /* Read device revision and ID */
 361         dm_i2c_read(dev, 1, &reg, 1);
 362         debug("Retimer version id = 0x%x\n", reg);
 363
 364         /* Enable Broadcast. All writes target all channel register sets */
 365         reg = 0x0c;
 366         dm_i2c_write(dev, 0xff, &reg, 1);
 367
 368         /* Reset Channel Registers */
 369         dm_i2c_read(dev, 0, &reg, 1);
 370         reg |= 0x4;
 371         dm_i2c_write(dev, 0, &reg, 1);
 372
 373         /* Enable override divider select and Enable Override Output Mux */
 374         dm_i2c_read(dev, 9, &reg, 1);
 375         reg |= 0x24;
 376         dm_i2c_write(dev, 9, &reg, 1);
 377
 378         /* Select VCO Divider to full rate (000) */
 379         dm_i2c_read(dev, 0x18, &reg, 1);
 380         reg &= 0x8f;
 381         dm_i2c_write(dev, 0x18, &reg, 1);
 382
 383         /* Selects active PFD MUX Input as Re-timed Data (001) */
 384         dm_i2c_read(dev, 0x1e, &reg, 1);
 385         reg &= 0x3f;
 386         reg |= 0x20;
 387         dm_i2c_write(dev, 0x1e, &reg, 1);
 388
 389         /* Set data rate as 10.3125 Gbps */
 390         reg = 0x0;
 391         dm_i2c_write(dev, 0x60, &reg, 1);
 392         reg = 0xb2;
 393         dm_i2c_write(dev, 0x61, &reg, 1);
 394         reg = 0x90;
 395         dm_i2c_write(dev, 0x62, &reg, 1);
 396         reg = 0xb3;
 397         dm_i2c_write(dev, 0x63, &reg, 1);
 398         reg = 0xcd;
 399         dm_i2c_write(dev, 0x64, &reg, 1);
 400 #else
 401         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 402
 403         /* Access to Control/Shared register */
 404         reg = 0x0;
 405         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 406
 407         /* Read device revision and ID */
 408         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 409         debug("Retimer version id = 0x%x\n", reg);
 410
 411         /* Enable Broadcast. All writes target all channel register sets */
 412         reg = 0x0c;
 413         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 414
 415         /* Reset Channel Registers */
 416         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 417         reg |= 0x4;
 418         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 419
 420         /* Enable override divider select and Enable Override Output Mux */
 421         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 422         reg |= 0x24;
 423         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 424
 425         /* Select VCO Divider to full rate (000) */
 426         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 427         reg &= 0x8f;
 428         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 429
 430         /* Selects active PFD MUX Input as Re-timed Data (001) */
 431         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 432         reg &= 0x3f;
 433         reg |= 0x20;
 434         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 435
 436         /* Set data rate as 10.3125 Gbps */
 437         reg = 0x0;
 438         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 439         reg = 0xb2;
 440         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 441         reg = 0x90;
 442         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 443         reg = 0xb3;
 444         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 445         reg = 0xcd;
 446         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 447 #endif
 448
 449         /* Return the default channel */
 450         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
 451 }
 452
 453 int board_early_init_f(void)
 454 {
 455 #ifdef CONFIG_HAS_FSL_XHCI_USB
 456         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 457         u32 usb_pwrfault;
 458 #endif
 459 #ifdef CONFIG_LPUART
 460         u8 uart;
 461 #endif
 462
 463 #ifdef CONFIG_SYS_I2C
 464 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 465         i2c_early_init_f();
 466 #endif
 467 #endif
 468         fsl_lsch2_early_init_f();
 469
 470 #ifdef CONFIG_HAS_FSL_XHCI_USB
 471         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 472         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 473         usb_pwrfault =
 474                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 475                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 476                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 477         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 478 #endif
 479
 480 #ifdef CONFIG_LPUART
 481         /* We use lpuart0 as system console */
 482         uart = QIXIS_READ(brdcfg[14]);
 483         uart &= ~CFG_UART_MUX_MASK;
 484         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 485         QIXIS_WRITE(brdcfg[14], uart);
 486 #endif
 487
 488         return 0;
 489 }
 490
 491 #ifdef CONFIG_FSL_DEEP_SLEEP
 492 /* determine if it is a warm boot */
 493 bool is_warm_boot(void)
 494 {
 495 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 496         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 497
 498         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 499                 return 1;
 500
 501         return 0;
 502 }
 503 #endif
 504
 505 int config_board_mux(int ctrl_type)
 506 {
 507         u8 reg14;
 508
 509         reg14 = QIXIS_READ(brdcfg[14]);
 510
 511         switch (ctrl_type) {
 512         case MUX_TYPE_GPIO:
 513                 reg14 = (reg14 & (~0x30)) | 0x20;
 514                 break;
 515         default:
 516                 puts("Unsupported mux interface type\n");
 517                 return -1;
 518         }
 519
 520         QIXIS_WRITE(brdcfg[14], reg14);
 521
 522         return 0;
 523 }
 524
 525 int config_serdes_mux(void)
 526 {
 527         return 0;
 528 }
 529
 530
 531 #ifdef CONFIG_MISC_INIT_R
 532 int misc_init_r(void)
 533 {
 534         if (hwconfig("gpio"))
 535                 config_board_mux(MUX_TYPE_GPIO);
 536
 537         return 0;
 538 }
 539 #endif
 540
 541 int board_init(void)
 542 {
 543 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 544         erratum_a010315();
 545 #endif
 546
 547         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 548         board_retimer_init();
 549
 550 #ifdef CONFIG_SYS_FSL_SERDES
 551         config_serdes_mux();
 552 #endif
 553
 554 #ifdef CONFIG_FSL_LS_PPA
 555         ppa_init();
 556 #endif
 557
 558         return 0;
 559 }
 560
 561 #ifdef CONFIG_OF_BOARD_SETUP
 562 int ft_board_setup(void *blob, bd_t *bd)
 563 {
 564         u64 base[CONFIG_NR_DRAM_BANKS];
 565         u64 size[CONFIG_NR_DRAM_BANKS];
 566         u8 reg;
 567
 568         /* fixup DT for the two DDR banks */
 569         base[0] = gd->bd->bi_dram[0].start;
 570         size[0] = gd->bd->bi_dram[0].size;
 571         base[1] = gd->bd->bi_dram[1].start;
 572         size[1] = gd->bd->bi_dram[1].size;
 573
 574         fdt_fixup_memory_banks(blob, base, size, 2);
 575         ft_cpu_setup(blob, bd);
 576
 577 #ifdef CONFIG_SYS_DPAA_FMAN
 578         fdt_fixup_fman_ethernet(blob);
 579         fdt_fixup_board_enet(blob);
 580 #endif
 581
 582         fdt_fixup_icid(blob);
 583
 584         reg = QIXIS_READ(brdcfg[0]);
 585         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 586
 587         /* Disable IFC if QSPI is enabled */
 588         if (reg == 0xF)
 589                 do_fixup_by_compat(blob, "fsl,ifc",
 590                                    "status", "disabled", 8 + 1, 1);
 591
 592         return 0;
 593 }
 594 #endif
 595
 596 u8 flash_read8(void *addr)
 597 {
 598         return __raw_readb(addr + 1);
 599 }
 600
 601 void flash_write16(u16 val, void *addr)
 602 {
 603         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 604
 605         __raw_writew(shftval, addr);
 606 }
 607
 608 u16 flash_read16(void *addr)
 609 {
 610         u16 val = __raw_readw(addr);
 611
 612         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 613 }
 614
 615 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 616 void *env_sf_get_env_addr(void)
 617 {
 618         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 619 }
 620 #endif