1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
9 #include <fdt_support.h>
10 #include <fsl_ddr_sdram.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ppa.h>
15 #include <asm/arch/fdt.h>
16 #include <asm/arch/mmu.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include <asm/arch-fsl-layerscape/fsl_icid.h>
25 #include <fsl_esdhc.h>
29 #include "../common/qixis.h"
30 #include "ls1043aqds_qixis.h"
32 DECLARE_GLOBAL_DATA_PTR;
38 /* LS1043AQDS serdes mux */
39 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
40 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
41 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
42 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
43 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
44 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
45 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
46 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
47 #define CFG_UART_MUX_MASK 0x6
48 #define CFG_UART_MUX_SHIFT 1
49 #define CFG_LPUART_EN 0x1
52 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
56 CONFIG_SYS_NOR0_CSPR_EXT,
70 CONFIG_SYS_NOR1_CSPR_EXT,
83 CONFIG_SYS_NAND_CSPR_EXT,
84 CONFIG_SYS_NAND_AMASK,
87 CONFIG_SYS_NAND_FTIM0,
88 CONFIG_SYS_NAND_FTIM1,
89 CONFIG_SYS_NAND_FTIM2,
96 CONFIG_SYS_FPGA_CSPR_EXT,
97 CONFIG_SYS_FPGA_AMASK,
100 CONFIG_SYS_FPGA_FTIM0,
101 CONFIG_SYS_FPGA_FTIM1,
102 CONFIG_SYS_FPGA_FTIM2,
103 CONFIG_SYS_FPGA_FTIM3
108 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
111 CONFIG_SYS_NAND_CSPR,
112 CONFIG_SYS_NAND_CSPR_EXT,
113 CONFIG_SYS_NAND_AMASK,
114 CONFIG_SYS_NAND_CSOR,
116 CONFIG_SYS_NAND_FTIM0,
117 CONFIG_SYS_NAND_FTIM1,
118 CONFIG_SYS_NAND_FTIM2,
119 CONFIG_SYS_NAND_FTIM3
124 CONFIG_SYS_NOR0_CSPR,
125 CONFIG_SYS_NOR0_CSPR_EXT,
126 CONFIG_SYS_NOR_AMASK,
129 CONFIG_SYS_NOR_FTIM0,
130 CONFIG_SYS_NOR_FTIM1,
131 CONFIG_SYS_NOR_FTIM2,
137 CONFIG_SYS_NOR1_CSPR,
138 CONFIG_SYS_NOR1_CSPR_EXT,
139 CONFIG_SYS_NOR_AMASK,
142 CONFIG_SYS_NOR_FTIM0,
143 CONFIG_SYS_NOR_FTIM1,
144 CONFIG_SYS_NOR_FTIM2,
150 CONFIG_SYS_FPGA_CSPR,
151 CONFIG_SYS_FPGA_CSPR_EXT,
152 CONFIG_SYS_FPGA_AMASK,
153 CONFIG_SYS_FPGA_CSOR,
155 CONFIG_SYS_FPGA_FTIM0,
156 CONFIG_SYS_FPGA_FTIM1,
157 CONFIG_SYS_FPGA_FTIM2,
158 CONFIG_SYS_FPGA_FTIM3
163 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
165 enum boot_src src = get_boot_src();
167 if (src == BOOT_SOURCE_IFC_NAND)
168 regs_info->regs = ifc_cfg_nand_boot;
170 regs_info->regs = ifc_cfg_nor_boot;
171 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
177 #ifdef CONFIG_TFABOOT
178 enum boot_src src = get_boot_src();
181 #ifndef CONFIG_SD_BOOT
185 puts("Board: LS1043AQDS, boot from ");
187 #ifdef CONFIG_TFABOOT
188 if (src == BOOT_SOURCE_SD_MMC)
193 #ifdef CONFIG_SD_BOOT
196 sw = QIXIS_READ(brdcfg[0]);
197 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
200 printf("vBank: %d\n", sw);
208 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
211 #ifdef CONFIG_TFABOOT
214 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
215 QIXIS_READ(id), QIXIS_READ(arch));
217 printf("FPGA: v%d (%s), build %d\n",
218 (int)QIXIS_READ(scver), qixis_read_tag(buf),
219 (int)qixis_read_minor());
224 bool if_board_diff_clk(void)
226 u8 diff_conf = QIXIS_READ(brdcfg[11]);
228 return diff_conf & 0x40;
231 unsigned long get_board_sys_clk(void)
233 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
235 switch (sysclk_conf & 0x0f) {
236 case QIXIS_SYSCLK_64:
238 case QIXIS_SYSCLK_83:
240 case QIXIS_SYSCLK_100:
242 case QIXIS_SYSCLK_125:
244 case QIXIS_SYSCLK_133:
246 case QIXIS_SYSCLK_150:
248 case QIXIS_SYSCLK_160:
250 case QIXIS_SYSCLK_166:
257 unsigned long get_board_ddr_clk(void)
259 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
261 if (if_board_diff_clk())
262 return get_board_sys_clk();
263 switch ((ddrclk_conf & 0x30) >> 4) {
264 case QIXIS_DDRCLK_100:
266 case QIXIS_DDRCLK_125:
268 case QIXIS_DDRCLK_133:
275 int select_i2c_ch_pca9547(u8 ch, int bus_num)
282 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
285 printf("%s: Cannot find udev for a bus %d\n", __func__,
289 ret = dm_i2c_write(dev, 0, &ch, 1);
291 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
294 puts("PCA: failed to select proper channel\n");
304 * When resuming from deep sleep, the I2C channel may not be
305 * in the default channel. So, switch to the default channel
306 * before accessing DDR SPD.
308 * PCA9547 mount on I2C1 bus
310 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
312 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
313 defined(CONFIG_SPL_BUILD)
314 /* This will break-before-make MMU for DDR */
315 update_early_mmu_table();
321 int i2c_multiplexer_select_vid_channel(u8 channel)
323 return select_i2c_ch_pca9547(channel, 0);
326 void board_retimer_init(void)
331 /* Retimer is connected to I2C1_CH7_CH5 */
332 select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
338 ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
341 printf("%s: Cannot find udev for a bus %d\n", __func__,
345 dm_i2c_write(dev, 0, ®, 1);
347 /* Access to Control/Shared register */
348 ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
351 printf("%s: Cannot find udev for a bus %d\n", __func__,
357 dm_i2c_write(dev, 0xff, ®, 1);
359 /* Read device revision and ID */
360 dm_i2c_read(dev, 1, ®, 1);
361 debug("Retimer version id = 0x%x\n", reg);
363 /* Enable Broadcast. All writes target all channel register sets */
365 dm_i2c_write(dev, 0xff, ®, 1);
367 /* Reset Channel Registers */
368 dm_i2c_read(dev, 0, ®, 1);
370 dm_i2c_write(dev, 0, ®, 1);
372 /* Enable override divider select and Enable Override Output Mux */
373 dm_i2c_read(dev, 9, ®, 1);
375 dm_i2c_write(dev, 9, ®, 1);
377 /* Select VCO Divider to full rate (000) */
378 dm_i2c_read(dev, 0x18, ®, 1);
380 dm_i2c_write(dev, 0x18, ®, 1);
382 /* Selects active PFD MUX Input as Re-timed Data (001) */
383 dm_i2c_read(dev, 0x1e, ®, 1);
386 dm_i2c_write(dev, 0x1e, ®, 1);
388 /* Set data rate as 10.3125 Gbps */
390 dm_i2c_write(dev, 0x60, ®, 1);
392 dm_i2c_write(dev, 0x61, ®, 1);
394 dm_i2c_write(dev, 0x62, ®, 1);
396 dm_i2c_write(dev, 0x63, ®, 1);
398 dm_i2c_write(dev, 0x64, ®, 1);
400 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
402 /* Access to Control/Shared register */
404 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
406 /* Read device revision and ID */
407 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
408 debug("Retimer version id = 0x%x\n", reg);
410 /* Enable Broadcast. All writes target all channel register sets */
412 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
414 /* Reset Channel Registers */
415 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
417 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
419 /* Enable override divider select and Enable Override Output Mux */
420 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
422 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
424 /* Select VCO Divider to full rate (000) */
425 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
427 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
429 /* Selects active PFD MUX Input as Re-timed Data (001) */
430 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
433 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
435 /* Set data rate as 10.3125 Gbps */
437 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
439 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
441 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
443 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
445 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
448 /* Return the default channel */
449 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
452 int board_early_init_f(void)
454 #ifdef CONFIG_HAS_FSL_XHCI_USB
455 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
462 #ifdef CONFIG_SYS_I2C
463 #ifdef CONFIG_SYS_I2C_EARLY_INIT
467 fsl_lsch2_early_init_f();
469 #ifdef CONFIG_HAS_FSL_XHCI_USB
470 out_be32(&scfg->rcwpmuxcr0, 0x3333);
471 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
473 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
474 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
475 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
476 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
480 /* We use lpuart0 as system console */
481 uart = QIXIS_READ(brdcfg[14]);
482 uart &= ~CFG_UART_MUX_MASK;
483 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
484 QIXIS_WRITE(brdcfg[14], uart);
490 #ifdef CONFIG_FSL_DEEP_SLEEP
491 /* determine if it is a warm boot */
492 bool is_warm_boot(void)
494 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
495 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
497 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
504 int config_board_mux(int ctrl_type)
508 reg14 = QIXIS_READ(brdcfg[14]);
512 reg14 = (reg14 & (~0x30)) | 0x20;
515 puts("Unsupported mux interface type\n");
519 QIXIS_WRITE(brdcfg[14], reg14);
524 int config_serdes_mux(void)
530 #ifdef CONFIG_MISC_INIT_R
531 int misc_init_r(void)
533 if (hwconfig("gpio"))
534 config_board_mux(MUX_TYPE_GPIO);
542 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
546 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
547 board_retimer_init();
549 #ifdef CONFIG_SYS_FSL_SERDES
553 #ifdef CONFIG_FSL_LS_PPA
560 #ifdef CONFIG_OF_BOARD_SETUP
561 int ft_board_setup(void *blob, bd_t *bd)
563 u64 base[CONFIG_NR_DRAM_BANKS];
564 u64 size[CONFIG_NR_DRAM_BANKS];
567 /* fixup DT for the two DDR banks */
568 base[0] = gd->bd->bi_dram[0].start;
569 size[0] = gd->bd->bi_dram[0].size;
570 base[1] = gd->bd->bi_dram[1].start;
571 size[1] = gd->bd->bi_dram[1].size;
573 fdt_fixup_memory_banks(blob, base, size, 2);
574 ft_cpu_setup(blob, bd);
576 #ifdef CONFIG_SYS_DPAA_FMAN
577 fdt_fixup_fman_ethernet(blob);
578 fdt_fixup_board_enet(blob);
581 fdt_fixup_icid(blob);
583 reg = QIXIS_READ(brdcfg[0]);
584 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
586 /* Disable IFC if QSPI is enabled */
588 do_fixup_by_compat(blob, "fsl,ifc",
589 "status", "disabled", 8 + 1, 1);
595 u8 flash_read8(void *addr)
597 return __raw_readb(addr + 1);
600 void flash_write16(u16 val, void *addr)
602 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
604 __raw_writew(shftval, addr);
607 u16 flash_read16(void *addr)
609 u16 val = __raw_readw(addr);
611 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
614 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
615 void *env_sf_get_env_addr(void)
617 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);