board/freescale/ls1043aqds/ls1043aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/ppa.h>
  17 #include <asm/arch/fdt.h>
  18 #include <asm/arch/mmu.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/soc.h>
  21 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  22 #include <ahci.h>
  23 #include <hwconfig.h>
  24 #include <mmc.h>
  25 #include <scsi.h>
  26 #include <fm_eth.h>
  27 #include <fsl_esdhc.h>
  28 #include <fsl_ifc.h>
  29 #include <spl.h>
  30
  31 #include "../common/qixis.h"
  32 #include "ls1043aqds_qixis.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 enum {
  37         MUX_TYPE_GPIO,
  38 };
  39
  40 /* LS1043AQDS serdes mux */
  41 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  42 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  43 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  44 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  45 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  46 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  47 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  48 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  49 #define CFG_UART_MUX_MASK       0x6
  50 #define CFG_UART_MUX_SHIFT      1
  51 #define CFG_LPUART_EN           0x1
  52
  53 #ifdef CONFIG_TFABOOT
  54 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  55         {
  56                 "nor0",
  57                 CONFIG_SYS_NOR0_CSPR,
  58                 CONFIG_SYS_NOR0_CSPR_EXT,
  59                 CONFIG_SYS_NOR_AMASK,
  60                 CONFIG_SYS_NOR_CSOR,
  61                 {
  62                         CONFIG_SYS_NOR_FTIM0,
  63                         CONFIG_SYS_NOR_FTIM1,
  64                         CONFIG_SYS_NOR_FTIM2,
  65                         CONFIG_SYS_NOR_FTIM3
  66                 },
  67
  68         },
  69         {
  70                 "nor1",
  71                 CONFIG_SYS_NOR1_CSPR,
  72                 CONFIG_SYS_NOR1_CSPR_EXT,
  73                 CONFIG_SYS_NOR_AMASK,
  74                 CONFIG_SYS_NOR_CSOR,
  75                 {
  76                         CONFIG_SYS_NOR_FTIM0,
  77                         CONFIG_SYS_NOR_FTIM1,
  78                         CONFIG_SYS_NOR_FTIM2,
  79                         CONFIG_SYS_NOR_FTIM3
  80                 },
  81         },
  82         {
  83                 "nand",
  84                 CONFIG_SYS_NAND_CSPR,
  85                 CONFIG_SYS_NAND_CSPR_EXT,
  86                 CONFIG_SYS_NAND_AMASK,
  87                 CONFIG_SYS_NAND_CSOR,
  88                 {
  89                         CONFIG_SYS_NAND_FTIM0,
  90                         CONFIG_SYS_NAND_FTIM1,
  91                         CONFIG_SYS_NAND_FTIM2,
  92                         CONFIG_SYS_NAND_FTIM3
  93                 },
  94         },
  95         {
  96                 "fpga",
  97                 CONFIG_SYS_FPGA_CSPR,
  98                 CONFIG_SYS_FPGA_CSPR_EXT,
  99                 CONFIG_SYS_FPGA_AMASK,
 100                 CONFIG_SYS_FPGA_CSOR,
 101                 {
 102                         CONFIG_SYS_FPGA_FTIM0,
 103                         CONFIG_SYS_FPGA_FTIM1,
 104                         CONFIG_SYS_FPGA_FTIM2,
 105                         CONFIG_SYS_FPGA_FTIM3
 106                 },
 107         }
 108 };
 109
 110 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 111         {
 112                 "nand",
 113                 CONFIG_SYS_NAND_CSPR,
 114                 CONFIG_SYS_NAND_CSPR_EXT,
 115                 CONFIG_SYS_NAND_AMASK,
 116                 CONFIG_SYS_NAND_CSOR,
 117                 {
 118                         CONFIG_SYS_NAND_FTIM0,
 119                         CONFIG_SYS_NAND_FTIM1,
 120                         CONFIG_SYS_NAND_FTIM2,
 121                         CONFIG_SYS_NAND_FTIM3
 122                 },
 123         },
 124         {
 125                 "nor0",
 126                 CONFIG_SYS_NOR0_CSPR,
 127                 CONFIG_SYS_NOR0_CSPR_EXT,
 128                 CONFIG_SYS_NOR_AMASK,
 129                 CONFIG_SYS_NOR_CSOR,
 130                 {
 131                         CONFIG_SYS_NOR_FTIM0,
 132                         CONFIG_SYS_NOR_FTIM1,
 133                         CONFIG_SYS_NOR_FTIM2,
 134                         CONFIG_SYS_NOR_FTIM3
 135                 },
 136         },
 137         {
 138                 "nor1",
 139                 CONFIG_SYS_NOR1_CSPR,
 140                 CONFIG_SYS_NOR1_CSPR_EXT,
 141                 CONFIG_SYS_NOR_AMASK,
 142                 CONFIG_SYS_NOR_CSOR,
 143                 {
 144                         CONFIG_SYS_NOR_FTIM0,
 145                         CONFIG_SYS_NOR_FTIM1,
 146                         CONFIG_SYS_NOR_FTIM2,
 147                         CONFIG_SYS_NOR_FTIM3
 148                 },
 149         },
 150         {
 151                 "fpga",
 152                 CONFIG_SYS_FPGA_CSPR,
 153                 CONFIG_SYS_FPGA_CSPR_EXT,
 154                 CONFIG_SYS_FPGA_AMASK,
 155                 CONFIG_SYS_FPGA_CSOR,
 156                 {
 157                         CONFIG_SYS_FPGA_FTIM0,
 158                         CONFIG_SYS_FPGA_FTIM1,
 159                         CONFIG_SYS_FPGA_FTIM2,
 160                         CONFIG_SYS_FPGA_FTIM3
 161                 },
 162         }
 163 };
 164
 165 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 166 {
 167         enum boot_src src = get_boot_src();
 168
 169         if (src == BOOT_SOURCE_IFC_NAND)
 170                 regs_info->regs = ifc_cfg_nand_boot;
 171         else
 172                 regs_info->regs = ifc_cfg_nor_boot;
 173         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 174 }
 175 #endif
 176
 177 int checkboard(void)
 178 {
 179 #ifdef CONFIG_TFABOOT
 180         enum boot_src src = get_boot_src();
 181 #endif
 182         char buf[64];
 183 #ifndef CONFIG_SD_BOOT
 184         u8 sw;
 185 #endif
 186
 187         puts("Board: LS1043AQDS, boot from ");
 188
 189 #ifdef CONFIG_TFABOOT
 190         if (src == BOOT_SOURCE_SD_MMC)
 191                 puts("SD\n");
 192         else {
 193 #endif
 194
 195 #ifdef CONFIG_SD_BOOT
 196         puts("SD\n");
 197 #else
 198         sw = QIXIS_READ(brdcfg[0]);
 199         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 200
 201         if (sw < 0x8)
 202                 printf("vBank: %d\n", sw);
 203         else if (sw == 0x8)
 204                 puts("PromJet\n");
 205         else if (sw == 0x9)
 206                 puts("NAND\n");
 207         else if (sw == 0xF)
 208                 printf("QSPI\n");
 209         else
 210                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 211 #endif
 212
 213 #ifdef CONFIG_TFABOOT
 214         }
 215 #endif
 216         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 217                QIXIS_READ(id), QIXIS_READ(arch));
 218
 219         printf("FPGA:  v%d (%s), build %d\n",
 220                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 221                (int)qixis_read_minor());
 222
 223         return 0;
 224 }
 225
 226 bool if_board_diff_clk(void)
 227 {
 228         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 229
 230         return diff_conf & 0x40;
 231 }
 232
 233 unsigned long get_board_sys_clk(void)
 234 {
 235         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 236
 237         switch (sysclk_conf & 0x0f) {
 238         case QIXIS_SYSCLK_64:
 239                 return 64000000;
 240         case QIXIS_SYSCLK_83:
 241                 return 83333333;
 242         case QIXIS_SYSCLK_100:
 243                 return 100000000;
 244         case QIXIS_SYSCLK_125:
 245                 return 125000000;
 246         case QIXIS_SYSCLK_133:
 247                 return 133333333;
 248         case QIXIS_SYSCLK_150:
 249                 return 150000000;
 250         case QIXIS_SYSCLK_160:
 251                 return 160000000;
 252         case QIXIS_SYSCLK_166:
 253                 return 166666666;
 254         }
 255
 256         return 66666666;
 257 }
 258
 259 unsigned long get_board_ddr_clk(void)
 260 {
 261         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 262
 263         if (if_board_diff_clk())
 264                 return get_board_sys_clk();
 265         switch ((ddrclk_conf & 0x30) >> 4) {
 266         case QIXIS_DDRCLK_100:
 267                 return 100000000;
 268         case QIXIS_DDRCLK_125:
 269                 return 125000000;
 270         case QIXIS_DDRCLK_133:
 271                 return 133333333;
 272         }
 273
 274         return 66666666;
 275 }
 276
 277 int select_i2c_ch_pca9547(u8 ch, int bus_num)
 278 {
 279         int ret;
 280
 281 #ifdef CONFIG_DM_I2C
 282         struct udevice *dev;
 283
 284         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
 285                                       1, &dev);
 286         if (ret) {
 287                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 288                        bus_num);
 289                 return ret;
 290         }
 291         ret = dm_i2c_write(dev, 0, &ch, 1);
 292 #else
 293         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 294 #endif
 295         if (ret) {
 296                 puts("PCA: failed to select proper channel\n");
 297                 return ret;
 298         }
 299
 300         return 0;
 301 }
 302
 303 int dram_init(void)
 304 {
 305         /*
 306          * When resuming from deep sleep, the I2C channel may not be
 307          * in the default channel. So, switch to the default channel
 308          * before accessing DDR SPD.
 309          *
 310          * PCA9547 mount on I2C1 bus
 311          */
 312         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 313         fsl_initdram();
 314 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 315         defined(CONFIG_SPL_BUILD)
 316         /* This will break-before-make MMU for DDR */
 317         update_early_mmu_table();
 318 #endif
 319
 320         return 0;
 321 }
 322
 323 int i2c_multiplexer_select_vid_channel(u8 channel)
 324 {
 325         return select_i2c_ch_pca9547(channel, 0);
 326 }
 327
 328 void board_retimer_init(void)
 329 {
 330         u8 reg;
 331         int bus_num = 0;
 332
 333         /* Retimer is connected to I2C1_CH7_CH5 */
 334         select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
 335         reg = I2C_MUX_CH5;
 336 #ifdef CONFIG_DM_I2C
 337         struct udevice *dev;
 338         int ret;
 339
 340         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
 341                                       1, &dev);
 342         if (ret) {
 343                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 344                        bus_num);
 345                 return;
 346         }
 347         dm_i2c_write(dev, 0, &reg, 1);
 348
 349         /* Access to Control/Shared register */
 350         ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
 351                                       1, &dev);
 352         if (ret) {
 353                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 354                        bus_num);
 355                 return;
 356         }
 357
 358         reg = 0x0;
 359         dm_i2c_write(dev, 0xff, &reg, 1);
 360
 361         /* Read device revision and ID */
 362         dm_i2c_read(dev, 1, &reg, 1);
 363         debug("Retimer version id = 0x%x\n", reg);
 364
 365         /* Enable Broadcast. All writes target all channel register sets */
 366         reg = 0x0c;
 367         dm_i2c_write(dev, 0xff, &reg, 1);
 368
 369         /* Reset Channel Registers */
 370         dm_i2c_read(dev, 0, &reg, 1);
 371         reg |= 0x4;
 372         dm_i2c_write(dev, 0, &reg, 1);
 373
 374         /* Enable override divider select and Enable Override Output Mux */
 375         dm_i2c_read(dev, 9, &reg, 1);
 376         reg |= 0x24;
 377         dm_i2c_write(dev, 9, &reg, 1);
 378
 379         /* Select VCO Divider to full rate (000) */
 380         dm_i2c_read(dev, 0x18, &reg, 1);
 381         reg &= 0x8f;
 382         dm_i2c_write(dev, 0x18, &reg, 1);
 383
 384         /* Selects active PFD MUX Input as Re-timed Data (001) */
 385         dm_i2c_read(dev, 0x1e, &reg, 1);
 386         reg &= 0x3f;
 387         reg |= 0x20;
 388         dm_i2c_write(dev, 0x1e, &reg, 1);
 389
 390         /* Set data rate as 10.3125 Gbps */
 391         reg = 0x0;
 392         dm_i2c_write(dev, 0x60, &reg, 1);
 393         reg = 0xb2;
 394         dm_i2c_write(dev, 0x61, &reg, 1);
 395         reg = 0x90;
 396         dm_i2c_write(dev, 0x62, &reg, 1);
 397         reg = 0xb3;
 398         dm_i2c_write(dev, 0x63, &reg, 1);
 399         reg = 0xcd;
 400         dm_i2c_write(dev, 0x64, &reg, 1);
 401 #else
 402         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 403
 404         /* Access to Control/Shared register */
 405         reg = 0x0;
 406         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 407
 408         /* Read device revision and ID */
 409         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 410         debug("Retimer version id = 0x%x\n", reg);
 411
 412         /* Enable Broadcast. All writes target all channel register sets */
 413         reg = 0x0c;
 414         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 415
 416         /* Reset Channel Registers */
 417         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 418         reg |= 0x4;
 419         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 420
 421         /* Enable override divider select and Enable Override Output Mux */
 422         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 423         reg |= 0x24;
 424         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 425
 426         /* Select VCO Divider to full rate (000) */
 427         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 428         reg &= 0x8f;
 429         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 430
 431         /* Selects active PFD MUX Input as Re-timed Data (001) */
 432         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 433         reg &= 0x3f;
 434         reg |= 0x20;
 435         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 436
 437         /* Set data rate as 10.3125 Gbps */
 438         reg = 0x0;
 439         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 440         reg = 0xb2;
 441         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 442         reg = 0x90;
 443         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 444         reg = 0xb3;
 445         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 446         reg = 0xcd;
 447         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 448 #endif
 449
 450         /* Return the default channel */
 451         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
 452 }
 453
 454 int board_early_init_f(void)
 455 {
 456         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 457 #ifdef CONFIG_HAS_FSL_XHCI_USB
 458         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 459         u32 usb_pwrfault;
 460 #endif
 461 #ifdef CONFIG_LPUART
 462         u8 uart;
 463 #endif
 464
 465         /*
 466          * Enable secure system counter for timer
 467          */
 468         out_le32(cntcr, 0x1);
 469
 470 #ifdef CONFIG_SYS_I2C
 471 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 472         i2c_early_init_f();
 473 #endif
 474 #endif
 475         fsl_lsch2_early_init_f();
 476
 477 #ifdef CONFIG_HAS_FSL_XHCI_USB
 478         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 479         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 480         usb_pwrfault =
 481                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 482                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 483                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 484         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 485 #endif
 486
 487 #ifdef CONFIG_LPUART
 488         /* We use lpuart0 as system console */
 489         uart = QIXIS_READ(brdcfg[14]);
 490         uart &= ~CFG_UART_MUX_MASK;
 491         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 492         QIXIS_WRITE(brdcfg[14], uart);
 493 #endif
 494
 495         return 0;
 496 }
 497
 498 #ifdef CONFIG_FSL_DEEP_SLEEP
 499 /* determine if it is a warm boot */
 500 bool is_warm_boot(void)
 501 {
 502 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 503         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 504
 505         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 506                 return 1;
 507
 508         return 0;
 509 }
 510 #endif
 511
 512 int config_board_mux(int ctrl_type)
 513 {
 514         u8 reg14;
 515
 516         reg14 = QIXIS_READ(brdcfg[14]);
 517
 518         switch (ctrl_type) {
 519         case MUX_TYPE_GPIO:
 520                 reg14 = (reg14 & (~0x30)) | 0x20;
 521                 break;
 522         default:
 523                 puts("Unsupported mux interface type\n");
 524                 return -1;
 525         }
 526
 527         QIXIS_WRITE(brdcfg[14], reg14);
 528
 529         return 0;
 530 }
 531
 532 int config_serdes_mux(void)
 533 {
 534         return 0;
 535 }
 536
 537
 538 #ifdef CONFIG_MISC_INIT_R
 539 int misc_init_r(void)
 540 {
 541         if (hwconfig("gpio"))
 542                 config_board_mux(MUX_TYPE_GPIO);
 543
 544         return 0;
 545 }
 546 #endif
 547
 548 int board_init(void)
 549 {
 550 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 551         erratum_a010315();
 552 #endif
 553
 554         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 555         board_retimer_init();
 556
 557 #ifdef CONFIG_SYS_FSL_SERDES
 558         config_serdes_mux();
 559 #endif
 560
 561 #ifdef CONFIG_FSL_LS_PPA
 562         ppa_init();
 563 #endif
 564
 565         return 0;
 566 }
 567
 568 #ifdef CONFIG_OF_BOARD_SETUP
 569 int ft_board_setup(void *blob, struct bd_info *bd)
 570 {
 571         u64 base[CONFIG_NR_DRAM_BANKS];
 572         u64 size[CONFIG_NR_DRAM_BANKS];
 573         u8 reg;
 574
 575         /* fixup DT for the two DDR banks */
 576         base[0] = gd->bd->bi_dram[0].start;
 577         size[0] = gd->bd->bi_dram[0].size;
 578         base[1] = gd->bd->bi_dram[1].start;
 579         size[1] = gd->bd->bi_dram[1].size;
 580
 581         fdt_fixup_memory_banks(blob, base, size, 2);
 582         ft_cpu_setup(blob, bd);
 583
 584 #ifdef CONFIG_SYS_DPAA_FMAN
 585 #ifndef CONFIG_DM_ETH
 586         fdt_fixup_fman_ethernet(blob);
 587 #endif
 588         fdt_fixup_board_enet(blob);
 589 #endif
 590
 591         fdt_fixup_icid(blob);
 592
 593         reg = QIXIS_READ(brdcfg[0]);
 594         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 595
 596         /* Disable IFC if QSPI is enabled */
 597         if (reg == 0xF)
 598                 do_fixup_by_compat(blob, "fsl,ifc",
 599                                    "status", "disabled", 8 + 1, 1);
 600
 601         return 0;
 602 }
 603 #endif
 604
 605 u8 flash_read8(void *addr)
 606 {
 607         return __raw_readb(addr + 1);
 608 }
 609
 610 void flash_write16(u16 val, void *addr)
 611 {
 612         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 613
 614         __raw_writew(shftval, addr);
 615 }
 616
 617 u16 flash_read16(void *addr)
 618 {
 619         u16 val = __raw_readw(addr);
 620
 621         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 622 }
 623
 624 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 625 void *env_sf_get_env_addr(void)
 626 {
 627         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 628 }
 629 #endif