board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <asm/io.h>
  11 #include <hwconfig.h>
  12 #include <fdt_support.h>
  13 #include <linux/libfdt.h>
  14 #include <env_internal.h>
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  17 #include <i2c.h>
  18 #include <asm/arch/soc.h>
  19 #ifdef CONFIG_FSL_LS_PPA
  20 #include <asm/arch/ppa.h>
  21 #endif
  22 #include <fsl_immap.h>
  23 #include <netdev.h>
  24
  25 #include <fdtdec.h>
  26 #include <miiphy.h>
  27 #include "../common/qixis.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int config_board_mux(void)
  32 {
  33 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  34         u8 reg;
  35
  36         reg = QIXIS_READ(brdcfg[13]);
  37         /* Field| Function
  38          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  39          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  40          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  41          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  42          */
  43         reg &= ~(0xf0);
  44         reg |= 0xb0;
  45         QIXIS_WRITE(brdcfg[13], reg);
  46
  47         reg = QIXIS_READ(brdcfg[15]);
  48         /* Field| Function
  49          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  50          * CAN1 | 0= CAN #1 transceiver enabled
  51          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  52          * CAN2 | 0= CAN #2 transceiver enabled
  53          */
  54         reg &= ~(0xc0);
  55         QIXIS_WRITE(brdcfg[15], reg);
  56 #endif
  57         return 0;
  58 }
  59
  60 int board_init(void)
  61 {
  62 #ifdef CONFIG_ENV_IS_NOWHERE
  63         gd->env_addr = (ulong)&default_environment[0];
  64 #endif
  65
  66 #ifdef CONFIG_FSL_CAAM
  67         sec_init();
  68 #endif
  69
  70 #ifdef CONFIG_FSL_LS_PPA
  71         ppa_init();
  72 #endif
  73
  74 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  75         pci_init();
  76 #endif
  77
  78 #if defined(CONFIG_TARGET_LS1028ARDB)
  79         u8 val = I2C_MUX_CH_DEFAULT;
  80
  81 #ifndef CONFIG_DM_I2C
  82         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  83 #else
  84         struct udevice *dev;
  85
  86         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  87                 dm_i2c_write(dev, 0x0b, &val, 1);
  88 #endif
  89 #endif
  90
  91 #if defined(CONFIG_TARGET_LS1028ARDB)
  92         u8 reg;
  93
  94         reg = QIXIS_READ(brdcfg[4]);
  95         /*
  96          * Field | Function
  97          * 3     | DisplayPort Power Enable (net DP_PWR_EN):
  98          * DPPWR | 0= DP_PWR is enabled.
  99          */
 100         reg &= ~(DP_PWD_EN_DEFAULT_MASK);
 101         QIXIS_WRITE(brdcfg[4], reg);
 102 #endif
 103         return 0;
 104 }
 105
 106 int board_eth_init(bd_t *bis)
 107 {
 108         return pci_eth_init(bis);
 109 }
 110
 111 #if defined(CONFIG_ARCH_MISC_INIT)
 112 int arch_misc_init(void)
 113 {
 114         config_board_mux();
 115
 116         return 0;
 117 }
 118 #endif
 119
 120 int board_early_init_f(void)
 121 {
 122 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 123         i2c_early_init_f();
 124 #endif
 125
 126         fsl_lsch3_early_init_f();
 127         return 0;
 128 }
 129
 130 void detail_board_ddr_info(void)
 131 {
 132         puts("\nDDR    ");
 133         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 134         print_ddr_info(0);
 135 }
 136
 137 #ifdef CONFIG_OF_BOARD_SETUP
 138 int ft_board_setup(void *blob, bd_t *bd)
 139 {
 140         u64 base[CONFIG_NR_DRAM_BANKS];
 141         u64 size[CONFIG_NR_DRAM_BANKS];
 142
 143         ft_cpu_setup(blob, bd);
 144
 145         /* fixup DT for the two GPP DDR banks */
 146         base[0] = gd->bd->bi_dram[0].start;
 147         size[0] = gd->bd->bi_dram[0].size;
 148         base[1] = gd->bd->bi_dram[1].start;
 149         size[1] = gd->bd->bi_dram[1].size;
 150
 151 #ifdef CONFIG_RESV_RAM
 152         /* reduce size if reserved memory is within this bank */
 153         if (gd->arch.resv_ram >= base[0] &&
 154             gd->arch.resv_ram < base[0] + size[0])
 155                 size[0] = gd->arch.resv_ram - base[0];
 156         else if (gd->arch.resv_ram >= base[1] &&
 157                  gd->arch.resv_ram < base[1] + size[1])
 158                 size[1] = gd->arch.resv_ram - base[1];
 159 #endif
 160
 161         fdt_fixup_memory_banks(blob, base, size, 2);
 162
 163         fdt_fixup_icid(blob);
 164
 165         return 0;
 166 }
 167 #endif
 168
 169 #ifdef CONFIG_FSL_QIXIS
 170 int checkboard(void)
 171 {
 172 #ifdef CONFIG_TFABOOT
 173         enum boot_src src = get_boot_src();
 174 #endif
 175         u8 sw;
 176
 177         int clock;
 178         char *board;
 179         char buf[64] = {0};
 180         static const char *freq[6] = {"100.00", "125.00", "156.25",
 181                                         "161.13", "322.26", "100.00 SS"};
 182
 183         cpu_name(buf);
 184         /* find the board details */
 185         sw = QIXIS_READ(id);
 186
 187         switch (sw) {
 188         case 0x46:
 189                 board = "QDS";
 190                 break;
 191         case 0x47:
 192                 board = "RDB";
 193                 break;
 194         case 0x49:
 195                 board = "HSSI";
 196                 break;
 197         default:
 198                 board = "unknown";
 199                 break;
 200         }
 201
 202         sw = QIXIS_READ(arch);
 203         printf("Board: %s-%s, Version: %c, boot from ",
 204                buf, board, (sw & 0xf) + 'A' - 1);
 205
 206         sw = QIXIS_READ(brdcfg[0]);
 207         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 208
 209 #ifdef CONFIG_TFABOOT
 210         if (src == BOOT_SOURCE_SD_MMC) {
 211                 puts("SD\n");
 212         } else if (src == BOOT_SOURCE_SD_MMC2) {
 213                 puts("eMMC\n");
 214         } else {
 215 #endif
 216 #ifdef CONFIG_SD_BOOT
 217                 puts("SD\n");
 218 #elif defined(CONFIG_EMMC_BOOT)
 219                 puts("eMMC\n");
 220 #else
 221                 switch (sw) {
 222                 case 0:
 223                 case 4:
 224                         printf("NOR\n");
 225                         break;
 226                 case 1:
 227                         printf("NAND\n");
 228                         break;
 229                 default:
 230                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 231                         break;
 232                 }
 233 #endif
 234 #ifdef CONFIG_TFABOOT
 235         }
 236 #endif
 237
 238         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 239         puts("SERDES1 Reference : ");
 240
 241         sw = QIXIS_READ(brdcfg[2]);
 242 #ifdef CONFIG_TARGET_LS1028ARDB
 243         clock = (sw >> 6) & 3;
 244 #else
 245         clock = (sw >> 4) & 0xf;
 246 #endif
 247
 248         printf("Clock1 = %sMHz ", freq[clock]);
 249 #ifdef CONFIG_TARGET_LS1028ARDB
 250         clock = (sw >> 4) & 3;
 251 #else
 252         clock = sw & 0xf;
 253 #endif
 254         printf("Clock2 = %sMHz\n", freq[clock]);
 255
 256         return 0;
 257 }
 258 #endif