1 // SPDX-License-Identifier: GPL-2.0+
12 #include <fdt_support.h>
13 #include <linux/libfdt.h>
14 #include <env_internal.h>
15 #include <asm/arch-fsl-layerscape/soc.h>
17 #include <asm/arch/soc.h>
18 #ifdef CONFIG_FSL_LS_PPA
19 #include <asm/arch/ppa.h>
21 #include <fsl_immap.h>
26 #include "../common/qixis.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 int config_board_mux(void)
32 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
35 reg = QIXIS_READ(brdcfg[13]);
37 * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
38 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
39 * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
40 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
44 QIXIS_WRITE(brdcfg[13], reg);
46 reg = QIXIS_READ(brdcfg[15]);
48 * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
49 * CAN1 | 0= CAN #1 transceiver enabled
50 * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
51 * CAN2 | 0= CAN #2 transceiver enabled
54 QIXIS_WRITE(brdcfg[15], reg);
61 #ifdef CONFIG_ENV_IS_NOWHERE
62 gd->env_addr = (ulong)&default_environment[0];
65 #ifdef CONFIG_FSL_LS_PPA
69 #ifndef CONFIG_SYS_EARLY_PCI_INIT
73 #if defined(CONFIG_TARGET_LS1028ARDB)
74 u8 val = I2C_MUX_CH_DEFAULT;
76 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
81 int board_eth_init(bd_t *bis)
83 return pci_eth_init(bis);
86 #if defined(CONFIG_ARCH_MISC_INIT)
87 int arch_misc_init(void)
95 int board_early_init_f(void)
97 #ifdef CONFIG_SYS_I2C_EARLY_INIT
101 fsl_lsch3_early_init_f();
105 void detail_board_ddr_info(void)
108 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
112 #ifdef CONFIG_OF_BOARD_SETUP
113 int ft_board_setup(void *blob, bd_t *bd)
115 u64 base[CONFIG_NR_DRAM_BANKS];
116 u64 size[CONFIG_NR_DRAM_BANKS];
118 ft_cpu_setup(blob, bd);
120 /* fixup DT for the two GPP DDR banks */
121 base[0] = gd->bd->bi_dram[0].start;
122 size[0] = gd->bd->bi_dram[0].size;
123 base[1] = gd->bd->bi_dram[1].start;
124 size[1] = gd->bd->bi_dram[1].size;
126 #ifdef CONFIG_RESV_RAM
127 /* reduce size if reserved memory is within this bank */
128 if (gd->arch.resv_ram >= base[0] &&
129 gd->arch.resv_ram < base[0] + size[0])
130 size[0] = gd->arch.resv_ram - base[0];
131 else if (gd->arch.resv_ram >= base[1] &&
132 gd->arch.resv_ram < base[1] + size[1])
133 size[1] = gd->arch.resv_ram - base[1];
136 fdt_fixup_memory_banks(blob, base, size, 2);
142 #ifdef CONFIG_FSL_QIXIS
145 #ifdef CONFIG_TFABOOT
146 enum boot_src src = get_boot_src();
153 static const char *freq[6] = {"100.00", "125.00", "156.25",
154 "161.13", "322.26", "100.00 SS"};
157 /* find the board details */
175 sw = QIXIS_READ(arch);
176 printf("Board: %s-%s, Version: %c, boot from ",
177 buf, board, (sw & 0xf) + 'A' - 1);
179 sw = QIXIS_READ(brdcfg[0]);
180 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
182 #ifdef CONFIG_TFABOOT
183 if (src == BOOT_SOURCE_SD_MMC) {
185 } else if (src == BOOT_SOURCE_SD_MMC2) {
189 #ifdef CONFIG_SD_BOOT
191 #elif defined(CONFIG_EMMC_BOOT)
203 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
207 #ifdef CONFIG_TFABOOT
211 printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
212 puts("SERDES1 Reference : ");
214 sw = QIXIS_READ(brdcfg[2]);
215 #ifdef CONFIG_TARGET_LS1028ARDB
216 clock = (sw >> 6) & 3;
218 clock = (sw >> 4) & 0xf;
221 printf("Clock1 = %sMHz ", freq[clock]);
222 #ifdef CONFIG_TARGET_LS1028ARDB
223 clock = (sw >> 4) & 3;
227 printf("Clock2 = %sMHz\n", freq[clock]);