board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <asm/io.h>
  11 #include <hwconfig.h>
  12 #include <fdt_support.h>
  13 #include <linux/libfdt.h>
  14 #include <environment.h>
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16 #include <i2c.h>
  17 #include <asm/arch/soc.h>
  18 #ifdef CONFIG_FSL_LS_PPA
  19 #include <asm/arch/ppa.h>
  20 #endif
  21 #include <fsl_immap.h>
  22 #include <netdev.h>
  23
  24 #include <fdtdec.h>
  25 #include <miiphy.h>
  26 #include "../common/qixis.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int config_board_mux(void)
  31 {
  32 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  33         u8 reg;
  34
  35         reg = QIXIS_READ(brdcfg[13]);
  36         /* Field| Function
  37          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  38          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  39          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  40          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  41          */
  42         reg &= ~(0xf0);
  43         reg |= 0xb0;
  44         QIXIS_WRITE(brdcfg[13], reg);
  45
  46         reg = QIXIS_READ(brdcfg[15]);
  47         /* Field| Function
  48          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  49          * CAN1 | 0= CAN #1 transceiver enabled
  50          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  51          * CAN2 | 0= CAN #2 transceiver enabled
  52          */
  53         reg &= ~(0xc0);
  54         QIXIS_WRITE(brdcfg[15], reg);
  55 #endif
  56         return 0;
  57 }
  58
  59 int board_init(void)
  60 {
  61 #ifdef CONFIG_ENV_IS_NOWHERE
  62         gd->env_addr = (ulong)&default_environment[0];
  63 #endif
  64
  65 #ifdef CONFIG_FSL_LS_PPA
  66         ppa_init();
  67 #endif
  68
  69 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  70         pci_init();
  71 #endif
  72
  73 #if defined(CONFIG_TARGET_LS1028ARDB)
  74         u8 val = I2C_MUX_CH_DEFAULT;
  75
  76         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  77 #endif
  78         return 0;
  79 }
  80
  81 int board_eth_init(bd_t *bis)
  82 {
  83         return pci_eth_init(bis);
  84 }
  85
  86 #if defined(CONFIG_ARCH_MISC_INIT)
  87 int arch_misc_init(void)
  88 {
  89         config_board_mux();
  90
  91         return 0;
  92 }
  93 #endif
  94
  95 int board_early_init_f(void)
  96 {
  97 #ifdef CONFIG_SYS_I2C_EARLY_INIT
  98         i2c_early_init_f();
  99 #endif
 100
 101         fsl_lsch3_early_init_f();
 102         return 0;
 103 }
 104
 105 void detail_board_ddr_info(void)
 106 {
 107         puts("\nDDR    ");
 108         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 109         print_ddr_info(0);
 110 }
 111
 112 #ifdef CONFIG_OF_BOARD_SETUP
 113 int ft_board_setup(void *blob, bd_t *bd)
 114 {
 115         u64 base[CONFIG_NR_DRAM_BANKS];
 116         u64 size[CONFIG_NR_DRAM_BANKS];
 117
 118         ft_cpu_setup(blob, bd);
 119
 120         /* fixup DT for the two GPP DDR banks */
 121         base[0] = gd->bd->bi_dram[0].start;
 122         size[0] = gd->bd->bi_dram[0].size;
 123         base[1] = gd->bd->bi_dram[1].start;
 124         size[1] = gd->bd->bi_dram[1].size;
 125
 126 #ifdef CONFIG_RESV_RAM
 127         /* reduce size if reserved memory is within this bank */
 128         if (gd->arch.resv_ram >= base[0] &&
 129             gd->arch.resv_ram < base[0] + size[0])
 130                 size[0] = gd->arch.resv_ram - base[0];
 131         else if (gd->arch.resv_ram >= base[1] &&
 132                  gd->arch.resv_ram < base[1] + size[1])
 133                 size[1] = gd->arch.resv_ram - base[1];
 134 #endif
 135
 136         fdt_fixup_memory_banks(blob, base, size, 2);
 137
 138         return 0;
 139 }
 140 #endif
 141
 142 #ifdef CONFIG_FSL_QIXIS
 143 int checkboard(void)
 144 {
 145 #ifdef CONFIG_TFABOOT
 146         enum boot_src src = get_boot_src();
 147 #endif
 148         u8 sw;
 149
 150         int clock;
 151         char *board;
 152         char buf[64] = {0};
 153         static const char *freq[6] = {"100.00", "125.00", "156.25",
 154                                         "161.13", "322.26", "100.00 SS"};
 155
 156         cpu_name(buf);
 157         /* find the board details */
 158         sw = QIXIS_READ(id);
 159
 160         switch (sw) {
 161         case 0x46:
 162                 board = "QDS";
 163                 break;
 164         case 0x47:
 165                 board = "RDB";
 166                 break;
 167         case 0x49:
 168                 board = "HSSI";
 169                 break;
 170         default:
 171                 board = "unknown";
 172                 break;
 173         }
 174
 175         sw = QIXIS_READ(arch);
 176         printf("Board: %s-%s, Version: %c, boot from ",
 177                buf, board, (sw & 0xf) + 'A' - 1);
 178
 179         sw = QIXIS_READ(brdcfg[0]);
 180         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 181
 182 #ifdef CONFIG_TFABOOT
 183         if (src == BOOT_SOURCE_SD_MMC) {
 184                 puts("SD\n");
 185         } else if (src == BOOT_SOURCE_SD_MMC2) {
 186                 puts("eMMC\n");
 187         } else {
 188 #endif
 189 #ifdef CONFIG_SD_BOOT
 190                 puts("SD\n");
 191 #elif defined(CONFIG_EMMC_BOOT)
 192                 puts("eMMC\n");
 193 #else
 194                 switch (sw) {
 195                 case 0:
 196                 case 4:
 197                         printf("NOR\n");
 198                         break;
 199                 case 1:
 200                         printf("NAND\n");
 201                         break;
 202                 default:
 203                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 204                         break;
 205                 }
 206 #endif
 207 #ifdef CONFIG_TFABOOT
 208         }
 209 #endif
 210
 211         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 212         puts("SERDES1 Reference : ");
 213
 214         sw = QIXIS_READ(brdcfg[2]);
 215 #ifdef CONFIG_TARGET_LS1028ARDB
 216         clock = (sw >> 6) & 3;
 217 #else
 218         clock = (sw >> 4) & 0xf;
 219 #endif
 220
 221         printf("Clock1 = %sMHz ", freq[clock]);
 222 #ifdef CONFIG_TARGET_LS1028ARDB
 223         clock = (sw >> 4) & 3;
 224 #else
 225         clock = sw & 0xf;
 226 #endif
 227         printf("Clock2 = %sMHz\n", freq[clock]);
 228
 229         return 0;
 230 }
 231 #endif