board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <malloc.h>
   9 #include <errno.h>
  10 #include <fsl_ddr.h>
  11 #include <net.h>
  12 #include <asm/io.h>
  13 #include <hwconfig.h>
  14 #include <fdt_support.h>
  15 #include <linux/libfdt.h>
  16 #include <env_internal.h>
  17 #include <asm/arch-fsl-layerscape/soc.h>
  18 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  19 #include <i2c.h>
  20 #include <asm/arch/soc.h>
  21 #ifdef CONFIG_FSL_LS_PPA
  22 #include <asm/arch/ppa.h>
  23 #endif
  24 #include <fsl_immap.h>
  25 #include <netdev.h>
  26
  27 #include <fdtdec.h>
  28 #include <miiphy.h>
  29 #include "../common/qixis.h"
  30 #include "../drivers/net/fsl_enetc.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 int config_board_mux(void)
  35 {
  36 #ifndef CONFIG_LPUART
  37 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  38         u8 reg;
  39
  40         reg = QIXIS_READ(brdcfg[13]);
  41         /* Field| Function
  42          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  43          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  44          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  45          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  46          */
  47         reg &= ~(0xf0);
  48         reg |= 0xb0;
  49         QIXIS_WRITE(brdcfg[13], reg);
  50
  51         reg = QIXIS_READ(brdcfg[15]);
  52         /* Field| Function
  53          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  54          * CAN1 | 0= CAN #1 transceiver enabled
  55          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  56          * CAN2 | 0= CAN #2 transceiver enabled
  57          */
  58         reg &= ~(0xc0);
  59         QIXIS_WRITE(brdcfg[15], reg);
  60 #endif
  61 #endif
  62
  63         return 0;
  64 }
  65
  66 #ifdef CONFIG_LPUART
  67 u32 get_lpuart_clk(void)
  68 {
  69         return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
  70 }
  71 #endif
  72
  73 int board_init(void)
  74 {
  75 #ifdef CONFIG_ENV_IS_NOWHERE
  76         gd->env_addr = (ulong)&default_environment[0];
  77 #endif
  78
  79 #ifdef CONFIG_FSL_CAAM
  80         sec_init();
  81 #endif
  82
  83 #ifdef CONFIG_FSL_LS_PPA
  84         ppa_init();
  85 #endif
  86
  87 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  88         pci_init();
  89 #endif
  90
  91 #if defined(CONFIG_TARGET_LS1028ARDB)
  92         u8 val = I2C_MUX_CH_DEFAULT;
  93
  94 #ifndef CONFIG_DM_I2C
  95         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  96 #else
  97         struct udevice *dev;
  98
  99         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
 100                 dm_i2c_write(dev, 0x0b, &val, 1);
 101 #endif
 102 #endif
 103
 104 #if defined(CONFIG_TARGET_LS1028ARDB)
 105         u8 reg;
 106
 107         reg = QIXIS_READ(brdcfg[4]);
 108         /*
 109          * Field | Function
 110          * 3     | DisplayPort Power Enable (net DP_PWR_EN):
 111          * DPPWR | 0= DP_PWR is enabled.
 112          */
 113         reg &= ~(DP_PWD_EN_DEFAULT_MASK);
 114         QIXIS_WRITE(brdcfg[4], reg);
 115 #endif
 116         return 0;
 117 }
 118
 119 int board_eth_init(struct bd_info *bis)
 120 {
 121         return pci_eth_init(bis);
 122 }
 123
 124 #ifdef CONFIG_MISC_INIT_R
 125 int misc_init_r(void)
 126 {
 127         config_board_mux();
 128
 129         return 0;
 130 }
 131 #endif
 132
 133 int board_early_init_f(void)
 134 {
 135 #ifdef CONFIG_LPUART
 136         u8 uart;
 137 #endif
 138
 139 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 140         i2c_early_init_f();
 141 #endif
 142
 143         fsl_lsch3_early_init_f();
 144
 145 #ifdef CONFIG_LPUART
 146         /*
 147          * Field| Function
 148          * --------------------------------------------------------------
 149          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
 150          * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
 151          * --------------------------------------------------------------
 152          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
 153          * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
 154          */
 155         /* use lpuart0 as system console */
 156         uart = QIXIS_READ(brdcfg[13]);
 157         uart &= ~CFG_LPUART_MUX_MASK;
 158         uart |= CFG_LPUART_EN;
 159         QIXIS_WRITE(brdcfg[13], uart);
 160 #endif
 161
 162         return 0;
 163 }
 164
 165 void detail_board_ddr_info(void)
 166 {
 167         puts("\nDDR    ");
 168         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 169         print_ddr_info(0);
 170 }
 171
 172 int esdhc_status_fixup(void *blob, const char *compat)
 173 {
 174         void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
 175         char esdhc1_path[] = "/soc/mmc@2140000";
 176         char esdhc2_path[] = "/soc/mmc@2150000";
 177         char dspi1_path[] = "/soc/spi@2100000";
 178         char dspi2_path[] = "/soc/spi@2110000";
 179         u32 mux_sdhc1, mux_sdhc2;
 180         u32 io = 0;
 181
 182         /*
 183          * The PMUX IO-expander for mux select is used to control
 184          * the muxing of various onboard interfaces.
 185          */
 186
 187         io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
 188         mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
 189
 190         /* Disable esdhc1/dspi1 if not selected. */
 191         if (mux_sdhc1 != 0)
 192                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 193                                  sizeof("disabled"), 1);
 194         if (mux_sdhc1 != 2)
 195                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 196                                  sizeof("disabled"), 1);
 197
 198         io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
 199         mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
 200
 201         /* Disable esdhc2/dspi2 if not selected. */
 202         if (mux_sdhc2 != 0)
 203                 do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
 204                                  sizeof("disabled"), 1);
 205         if (mux_sdhc2 != 2)
 206                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 207                                  sizeof("disabled"), 1);
 208
 209         return 0;
 210 }
 211
 212 #ifdef CONFIG_OF_BOARD_SETUP
 213 int ft_board_setup(void *blob, struct bd_info *bd)
 214 {
 215         u64 base[CONFIG_NR_DRAM_BANKS];
 216         u64 size[CONFIG_NR_DRAM_BANKS];
 217
 218         ft_cpu_setup(blob, bd);
 219
 220         /* fixup DT for the two GPP DDR banks */
 221         base[0] = gd->bd->bi_dram[0].start;
 222         size[0] = gd->bd->bi_dram[0].size;
 223         base[1] = gd->bd->bi_dram[1].start;
 224         size[1] = gd->bd->bi_dram[1].size;
 225
 226 #ifdef CONFIG_RESV_RAM
 227         /* reduce size if reserved memory is within this bank */
 228         if (gd->arch.resv_ram >= base[0] &&
 229             gd->arch.resv_ram < base[0] + size[0])
 230                 size[0] = gd->arch.resv_ram - base[0];
 231         else if (gd->arch.resv_ram >= base[1] &&
 232                  gd->arch.resv_ram < base[1] + size[1])
 233                 size[1] = gd->arch.resv_ram - base[1];
 234 #endif
 235
 236         fdt_fixup_memory_banks(blob, base, size, 2);
 237
 238         fdt_fixup_icid(blob);
 239
 240 #ifdef CONFIG_FSL_ENETC
 241         fdt_fixup_enetc_mac(blob);
 242 #endif
 243
 244         return 0;
 245 }
 246 #endif
 247
 248 #ifdef CONFIG_FSL_QIXIS
 249 int checkboard(void)
 250 {
 251 #ifdef CONFIG_TFABOOT
 252         enum boot_src src = get_boot_src();
 253 #endif
 254         u8 sw;
 255
 256         int clock;
 257         char *board;
 258         char buf[64] = {0};
 259         static const char *freq[6] = {"100.00", "125.00", "156.25",
 260                                         "161.13", "322.26", "100.00 SS"};
 261
 262         cpu_name(buf);
 263         /* find the board details */
 264         sw = QIXIS_READ(id);
 265
 266         switch (sw) {
 267         case 0x46:
 268                 board = "QDS";
 269                 break;
 270         case 0x47:
 271                 board = "RDB";
 272                 break;
 273         case 0x49:
 274                 board = "HSSI";
 275                 break;
 276         default:
 277                 board = "unknown";
 278                 break;
 279         }
 280
 281         sw = QIXIS_READ(arch);
 282         printf("Board: %s-%s, Version: %c, boot from ",
 283                buf, board, (sw & 0xf) + 'A' - 1);
 284
 285         sw = QIXIS_READ(brdcfg[0]);
 286         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 287
 288 #ifdef CONFIG_TFABOOT
 289         if (src == BOOT_SOURCE_SD_MMC) {
 290                 puts("SD\n");
 291         } else if (src == BOOT_SOURCE_SD_MMC2) {
 292                 puts("eMMC\n");
 293         } else {
 294 #endif
 295 #ifdef CONFIG_SD_BOOT
 296                 puts("SD\n");
 297 #elif defined(CONFIG_EMMC_BOOT)
 298                 puts("eMMC\n");
 299 #else
 300                 switch (sw) {
 301                 case 0:
 302                 case 4:
 303                         printf("NOR\n");
 304                         break;
 305                 case 1:
 306                         printf("NAND\n");
 307                         break;
 308                 default:
 309                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 310                         break;
 311                 }
 312 #endif
 313 #ifdef CONFIG_TFABOOT
 314         }
 315 #endif
 316
 317         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 318         puts("SERDES1 Reference : ");
 319
 320         sw = QIXIS_READ(brdcfg[2]);
 321 #ifdef CONFIG_TARGET_LS1028ARDB
 322         clock = (sw >> 6) & 3;
 323 #else
 324         clock = (sw >> 4) & 0xf;
 325 #endif
 326
 327         printf("Clock1 = %sMHz ", freq[clock]);
 328 #ifdef CONFIG_TARGET_LS1028ARDB
 329         clock = (sw >> 4) & 3;
 330 #else
 331         clock = sw & 0xf;
 332 #endif
 333         printf("Clock2 = %sMHz\n", freq[clock]);
 334
 335         return 0;
 336 }
 337 #endif