board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <asm/io.h>
  11 #include <hwconfig.h>
  12 #include <fdt_support.h>
  13 #include <linux/libfdt.h>
  14 #include <env_internal.h>
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  17 #include <i2c.h>
  18 #include <asm/arch/soc.h>
  19 #ifdef CONFIG_FSL_LS_PPA
  20 #include <asm/arch/ppa.h>
  21 #endif
  22 #include <fsl_immap.h>
  23 #include <netdev.h>
  24
  25 #include <fdtdec.h>
  26 #include <miiphy.h>
  27 #include "../common/qixis.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int config_board_mux(void)
  32 {
  33 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  34         u8 reg;
  35
  36         reg = QIXIS_READ(brdcfg[13]);
  37         /* Field| Function
  38          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  39          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  40          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  41          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  42          */
  43         reg &= ~(0xf0);
  44         reg |= 0xb0;
  45         QIXIS_WRITE(brdcfg[13], reg);
  46
  47         reg = QIXIS_READ(brdcfg[15]);
  48         /* Field| Function
  49          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  50          * CAN1 | 0= CAN #1 transceiver enabled
  51          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  52          * CAN2 | 0= CAN #2 transceiver enabled
  53          */
  54         reg &= ~(0xc0);
  55         QIXIS_WRITE(brdcfg[15], reg);
  56 #endif
  57         return 0;
  58 }
  59
  60 int board_init(void)
  61 {
  62 #ifdef CONFIG_ENV_IS_NOWHERE
  63         gd->env_addr = (ulong)&default_environment[0];
  64 #endif
  65
  66 #ifdef CONFIG_FSL_CAAM
  67         sec_init();
  68 #endif
  69
  70 #ifdef CONFIG_FSL_LS_PPA
  71         ppa_init();
  72 #endif
  73
  74 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  75         pci_init();
  76 #endif
  77
  78 #if defined(CONFIG_TARGET_LS1028ARDB)
  79         u8 val = I2C_MUX_CH_DEFAULT;
  80
  81 #ifndef CONFIG_DM_I2C
  82         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  83 #else
  84         struct udevice *dev;
  85
  86         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  87                 dm_i2c_write(dev, 0x0b, &val, 1);
  88 #endif
  89
  90 #endif
  91         return 0;
  92 }
  93
  94 int board_eth_init(bd_t *bis)
  95 {
  96         return pci_eth_init(bis);
  97 }
  98
  99 #if defined(CONFIG_ARCH_MISC_INIT)
 100 int arch_misc_init(void)
 101 {
 102         config_board_mux();
 103
 104         return 0;
 105 }
 106 #endif
 107
 108 int board_early_init_f(void)
 109 {
 110 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 111         i2c_early_init_f();
 112 #endif
 113
 114         fsl_lsch3_early_init_f();
 115         return 0;
 116 }
 117
 118 void detail_board_ddr_info(void)
 119 {
 120         puts("\nDDR    ");
 121         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 122         print_ddr_info(0);
 123 }
 124
 125 #ifdef CONFIG_OF_BOARD_SETUP
 126 int ft_board_setup(void *blob, bd_t *bd)
 127 {
 128         u64 base[CONFIG_NR_DRAM_BANKS];
 129         u64 size[CONFIG_NR_DRAM_BANKS];
 130
 131         ft_cpu_setup(blob, bd);
 132
 133         /* fixup DT for the two GPP DDR banks */
 134         base[0] = gd->bd->bi_dram[0].start;
 135         size[0] = gd->bd->bi_dram[0].size;
 136         base[1] = gd->bd->bi_dram[1].start;
 137         size[1] = gd->bd->bi_dram[1].size;
 138
 139 #ifdef CONFIG_RESV_RAM
 140         /* reduce size if reserved memory is within this bank */
 141         if (gd->arch.resv_ram >= base[0] &&
 142             gd->arch.resv_ram < base[0] + size[0])
 143                 size[0] = gd->arch.resv_ram - base[0];
 144         else if (gd->arch.resv_ram >= base[1] &&
 145                  gd->arch.resv_ram < base[1] + size[1])
 146                 size[1] = gd->arch.resv_ram - base[1];
 147 #endif
 148
 149         fdt_fixup_memory_banks(blob, base, size, 2);
 150
 151         fdt_fixup_icid(blob);
 152
 153         return 0;
 154 }
 155 #endif
 156
 157 #ifdef CONFIG_FSL_QIXIS
 158 int checkboard(void)
 159 {
 160 #ifdef CONFIG_TFABOOT
 161         enum boot_src src = get_boot_src();
 162 #endif
 163         u8 sw;
 164
 165         int clock;
 166         char *board;
 167         char buf[64] = {0};
 168         static const char *freq[6] = {"100.00", "125.00", "156.25",
 169                                         "161.13", "322.26", "100.00 SS"};
 170
 171         cpu_name(buf);
 172         /* find the board details */
 173         sw = QIXIS_READ(id);
 174
 175         switch (sw) {
 176         case 0x46:
 177                 board = "QDS";
 178                 break;
 179         case 0x47:
 180                 board = "RDB";
 181                 break;
 182         case 0x49:
 183                 board = "HSSI";
 184                 break;
 185         default:
 186                 board = "unknown";
 187                 break;
 188         }
 189
 190         sw = QIXIS_READ(arch);
 191         printf("Board: %s-%s, Version: %c, boot from ",
 192                buf, board, (sw & 0xf) + 'A' - 1);
 193
 194         sw = QIXIS_READ(brdcfg[0]);
 195         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 196
 197 #ifdef CONFIG_TFABOOT
 198         if (src == BOOT_SOURCE_SD_MMC) {
 199                 puts("SD\n");
 200         } else if (src == BOOT_SOURCE_SD_MMC2) {
 201                 puts("eMMC\n");
 202         } else {
 203 #endif
 204 #ifdef CONFIG_SD_BOOT
 205                 puts("SD\n");
 206 #elif defined(CONFIG_EMMC_BOOT)
 207                 puts("eMMC\n");
 208 #else
 209                 switch (sw) {
 210                 case 0:
 211                 case 4:
 212                         printf("NOR\n");
 213                         break;
 214                 case 1:
 215                         printf("NAND\n");
 216                         break;
 217                 default:
 218                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 219                         break;
 220                 }
 221 #endif
 222 #ifdef CONFIG_TFABOOT
 223         }
 224 #endif
 225
 226         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 227         puts("SERDES1 Reference : ");
 228
 229         sw = QIXIS_READ(brdcfg[2]);
 230 #ifdef CONFIG_TARGET_LS1028ARDB
 231         clock = (sw >> 6) & 3;
 232 #else
 233         clock = (sw >> 4) & 0xf;
 234 #endif
 235
 236         printf("Clock1 = %sMHz ", freq[clock]);
 237 #ifdef CONFIG_TARGET_LS1028ARDB
 238         clock = (sw >> 4) & 3;
 239 #else
 240         clock = sw & 0xf;
 241 #endif
 242         printf("Clock2 = %sMHz\n", freq[clock]);
 243
 244         return 0;
 245 }
 246 #endif