1 // SPDX-License-Identifier: GPL-2.0+
12 #include <fdt_support.h>
13 #include <linux/libfdt.h>
14 #include <env_internal.h>
15 #include <asm/arch-fsl-layerscape/soc.h>
16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
18 #include <asm/arch/soc.h>
19 #ifdef CONFIG_FSL_LS_PPA
20 #include <asm/arch/ppa.h>
22 #include <fsl_immap.h>
27 #include "../common/qixis.h"
28 #include "../drivers/net/fsl_enetc.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 int config_board_mux(void)
35 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
38 reg = QIXIS_READ(brdcfg[13]);
40 * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
41 * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
42 * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
43 * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
47 QIXIS_WRITE(brdcfg[13], reg);
49 reg = QIXIS_READ(brdcfg[15]);
51 * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
52 * CAN1 | 0= CAN #1 transceiver enabled
53 * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
54 * CAN2 | 0= CAN #2 transceiver enabled
57 QIXIS_WRITE(brdcfg[15], reg);
65 u32 get_lpuart_clk(void)
67 return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
73 #ifdef CONFIG_ENV_IS_NOWHERE
74 gd->env_addr = (ulong)&default_environment[0];
77 #ifdef CONFIG_FSL_CAAM
81 #ifdef CONFIG_FSL_LS_PPA
85 #ifndef CONFIG_SYS_EARLY_PCI_INIT
89 #if defined(CONFIG_TARGET_LS1028ARDB)
90 u8 val = I2C_MUX_CH_DEFAULT;
93 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
97 if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
98 dm_i2c_write(dev, 0x0b, &val, 1);
102 #if defined(CONFIG_TARGET_LS1028ARDB)
105 reg = QIXIS_READ(brdcfg[4]);
108 * 3 | DisplayPort Power Enable (net DP_PWR_EN):
109 * DPPWR | 0= DP_PWR is enabled.
111 reg &= ~(DP_PWD_EN_DEFAULT_MASK);
112 QIXIS_WRITE(brdcfg[4], reg);
117 int board_eth_init(bd_t *bis)
119 return pci_eth_init(bis);
122 #ifdef CONFIG_MISC_INIT_R
123 int misc_init_r(void)
131 int board_early_init_f(void)
137 #ifdef CONFIG_SYS_I2C_EARLY_INIT
141 fsl_lsch3_early_init_f();
146 * --------------------------------------------------------------
147 * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
148 * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
149 * --------------------------------------------------------------
150 * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
151 * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
153 /* use lpuart0 as system console */
154 uart = QIXIS_READ(brdcfg[13]);
155 uart &= ~CFG_LPUART_MUX_MASK;
156 uart |= CFG_LPUART_EN;
157 QIXIS_WRITE(brdcfg[13], uart);
163 void detail_board_ddr_info(void)
166 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
170 int esdhc_status_fixup(void *blob, const char *compat)
172 void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
173 char esdhc1_path[] = "/soc/mmc@2140000";
174 char esdhc2_path[] = "/soc/mmc@2150000";
175 char dspi1_path[] = "/soc/spi@2100000";
176 char dspi2_path[] = "/soc/spi@2110000";
177 u32 mux_sdhc1, mux_sdhc2;
181 * The PMUX IO-expander for mux select is used to control
182 * the muxing of various onboard interfaces.
185 io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
186 mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
188 /* Disable esdhc1/dspi1 if not selected. */
190 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
191 sizeof("disabled"), 1);
193 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
194 sizeof("disabled"), 1);
196 io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
197 mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
199 /* Disable esdhc2/dspi2 if not selected. */
201 do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
202 sizeof("disabled"), 1);
204 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
205 sizeof("disabled"), 1);
210 #ifdef CONFIG_OF_BOARD_SETUP
211 int ft_board_setup(void *blob, bd_t *bd)
213 u64 base[CONFIG_NR_DRAM_BANKS];
214 u64 size[CONFIG_NR_DRAM_BANKS];
216 ft_cpu_setup(blob, bd);
218 /* fixup DT for the two GPP DDR banks */
219 base[0] = gd->bd->bi_dram[0].start;
220 size[0] = gd->bd->bi_dram[0].size;
221 base[1] = gd->bd->bi_dram[1].start;
222 size[1] = gd->bd->bi_dram[1].size;
224 #ifdef CONFIG_RESV_RAM
225 /* reduce size if reserved memory is within this bank */
226 if (gd->arch.resv_ram >= base[0] &&
227 gd->arch.resv_ram < base[0] + size[0])
228 size[0] = gd->arch.resv_ram - base[0];
229 else if (gd->arch.resv_ram >= base[1] &&
230 gd->arch.resv_ram < base[1] + size[1])
231 size[1] = gd->arch.resv_ram - base[1];
234 fdt_fixup_memory_banks(blob, base, size, 2);
236 fdt_fixup_icid(blob);
238 #ifdef CONFIG_FSL_ENETC
239 fdt_fixup_enetc_mac(blob);
246 #ifdef CONFIG_FSL_QIXIS
249 #ifdef CONFIG_TFABOOT
250 enum boot_src src = get_boot_src();
257 static const char *freq[6] = {"100.00", "125.00", "156.25",
258 "161.13", "322.26", "100.00 SS"};
261 /* find the board details */
279 sw = QIXIS_READ(arch);
280 printf("Board: %s-%s, Version: %c, boot from ",
281 buf, board, (sw & 0xf) + 'A' - 1);
283 sw = QIXIS_READ(brdcfg[0]);
284 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
286 #ifdef CONFIG_TFABOOT
287 if (src == BOOT_SOURCE_SD_MMC) {
289 } else if (src == BOOT_SOURCE_SD_MMC2) {
293 #ifdef CONFIG_SD_BOOT
295 #elif defined(CONFIG_EMMC_BOOT)
307 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
311 #ifdef CONFIG_TFABOOT
315 printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
316 puts("SERDES1 Reference : ");
318 sw = QIXIS_READ(brdcfg[2]);
319 #ifdef CONFIG_TARGET_LS1028ARDB
320 clock = (sw >> 6) & 3;
322 clock = (sw >> 4) & 0xf;
325 printf("Clock1 = %sMHz ", freq[clock]);
326 #ifdef CONFIG_TARGET_LS1028ARDB
327 clock = (sw >> 4) & 3;
331 printf("Clock2 = %sMHz\n", freq[clock]);