board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <asm/io.h>
  11 #include <hwconfig.h>
  12 #include <fdt_support.h>
  13 #include <linux/libfdt.h>
  14 #include <env_internal.h>
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  17 #include <i2c.h>
  18 #include <asm/arch/soc.h>
  19 #ifdef CONFIG_FSL_LS_PPA
  20 #include <asm/arch/ppa.h>
  21 #endif
  22 #include <fsl_immap.h>
  23 #include <netdev.h>
  24
  25 #include <fdtdec.h>
  26 #include <miiphy.h>
  27 #include "../common/qixis.h"
  28 #include "../drivers/net/fsl_enetc.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 int config_board_mux(void)
  33 {
  34 #ifndef CONFIG_LPUART
  35 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  36         u8 reg;
  37
  38         reg = QIXIS_READ(brdcfg[13]);
  39         /* Field| Function
  40          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  41          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  42          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  43          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  44          */
  45         reg &= ~(0xf0);
  46         reg |= 0xb0;
  47         QIXIS_WRITE(brdcfg[13], reg);
  48
  49         reg = QIXIS_READ(brdcfg[15]);
  50         /* Field| Function
  51          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  52          * CAN1 | 0= CAN #1 transceiver enabled
  53          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  54          * CAN2 | 0= CAN #2 transceiver enabled
  55          */
  56         reg &= ~(0xc0);
  57         QIXIS_WRITE(brdcfg[15], reg);
  58 #endif
  59 #endif
  60
  61         return 0;
  62 }
  63
  64 #ifdef CONFIG_LPUART
  65 u32 get_lpuart_clk(void)
  66 {
  67         return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
  68 }
  69 #endif
  70
  71 int board_init(void)
  72 {
  73 #ifdef CONFIG_ENV_IS_NOWHERE
  74         gd->env_addr = (ulong)&default_environment[0];
  75 #endif
  76
  77 #ifdef CONFIG_FSL_CAAM
  78         sec_init();
  79 #endif
  80
  81 #ifdef CONFIG_FSL_LS_PPA
  82         ppa_init();
  83 #endif
  84
  85 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  86         pci_init();
  87 #endif
  88
  89 #if defined(CONFIG_TARGET_LS1028ARDB)
  90         u8 val = I2C_MUX_CH_DEFAULT;
  91
  92 #ifndef CONFIG_DM_I2C
  93         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  94 #else
  95         struct udevice *dev;
  96
  97         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  98                 dm_i2c_write(dev, 0x0b, &val, 1);
  99 #endif
 100 #endif
 101
 102 #if defined(CONFIG_TARGET_LS1028ARDB)
 103         u8 reg;
 104
 105         reg = QIXIS_READ(brdcfg[4]);
 106         /*
 107          * Field | Function
 108          * 3     | DisplayPort Power Enable (net DP_PWR_EN):
 109          * DPPWR | 0= DP_PWR is enabled.
 110          */
 111         reg &= ~(DP_PWD_EN_DEFAULT_MASK);
 112         QIXIS_WRITE(brdcfg[4], reg);
 113 #endif
 114         return 0;
 115 }
 116
 117 int board_eth_init(bd_t *bis)
 118 {
 119         return pci_eth_init(bis);
 120 }
 121
 122 #ifdef CONFIG_MISC_INIT_R
 123 int misc_init_r(void)
 124 {
 125         config_board_mux();
 126
 127         return 0;
 128 }
 129 #endif
 130
 131 int board_early_init_f(void)
 132 {
 133 #ifdef CONFIG_LPUART
 134         u8 uart;
 135 #endif
 136
 137 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 138         i2c_early_init_f();
 139 #endif
 140
 141         fsl_lsch3_early_init_f();
 142
 143 #ifdef CONFIG_LPUART
 144         /*
 145          * Field| Function
 146          * --------------------------------------------------------------
 147          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
 148          * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
 149          * --------------------------------------------------------------
 150          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
 151          * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
 152          */
 153         /* use lpuart0 as system console */
 154         uart = QIXIS_READ(brdcfg[13]);
 155         uart &= ~CFG_LPUART_MUX_MASK;
 156         uart |= CFG_LPUART_EN;
 157         QIXIS_WRITE(brdcfg[13], uart);
 158 #endif
 159
 160         return 0;
 161 }
 162
 163 void detail_board_ddr_info(void)
 164 {
 165         puts("\nDDR    ");
 166         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 167         print_ddr_info(0);
 168 }
 169
 170 int esdhc_status_fixup(void *blob, const char *compat)
 171 {
 172         void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
 173         char esdhc1_path[] = "/soc/mmc@2140000";
 174         char esdhc2_path[] = "/soc/mmc@2150000";
 175         char dspi1_path[] = "/soc/spi@2100000";
 176         char dspi2_path[] = "/soc/spi@2110000";
 177         u32 mux_sdhc1, mux_sdhc2;
 178         u32 io = 0;
 179
 180         /*
 181          * The PMUX IO-expander for mux select is used to control
 182          * the muxing of various onboard interfaces.
 183          */
 184
 185         io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
 186         mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
 187
 188         /* Disable esdhc1/dspi1 if not selected. */
 189         if (mux_sdhc1 != 0)
 190                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 191                                  sizeof("disabled"), 1);
 192         if (mux_sdhc1 != 2)
 193                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 194                                  sizeof("disabled"), 1);
 195
 196         io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
 197         mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
 198
 199         /* Disable esdhc2/dspi2 if not selected. */
 200         if (mux_sdhc2 != 0)
 201                 do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
 202                                  sizeof("disabled"), 1);
 203         if (mux_sdhc2 != 2)
 204                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 205                                  sizeof("disabled"), 1);
 206
 207         return 0;
 208 }
 209
 210 #ifdef CONFIG_OF_BOARD_SETUP
 211 int ft_board_setup(void *blob, bd_t *bd)
 212 {
 213         u64 base[CONFIG_NR_DRAM_BANKS];
 214         u64 size[CONFIG_NR_DRAM_BANKS];
 215
 216         ft_cpu_setup(blob, bd);
 217
 218         /* fixup DT for the two GPP DDR banks */
 219         base[0] = gd->bd->bi_dram[0].start;
 220         size[0] = gd->bd->bi_dram[0].size;
 221         base[1] = gd->bd->bi_dram[1].start;
 222         size[1] = gd->bd->bi_dram[1].size;
 223
 224 #ifdef CONFIG_RESV_RAM
 225         /* reduce size if reserved memory is within this bank */
 226         if (gd->arch.resv_ram >= base[0] &&
 227             gd->arch.resv_ram < base[0] + size[0])
 228                 size[0] = gd->arch.resv_ram - base[0];
 229         else if (gd->arch.resv_ram >= base[1] &&
 230                  gd->arch.resv_ram < base[1] + size[1])
 231                 size[1] = gd->arch.resv_ram - base[1];
 232 #endif
 233
 234         fdt_fixup_memory_banks(blob, base, size, 2);
 235
 236         fdt_fixup_icid(blob);
 237
 238 #ifdef CONFIG_FSL_ENETC
 239         fdt_fixup_enetc_mac(blob);
 240 #endif
 241
 242         return 0;
 243 }
 244 #endif
 245
 246 #ifdef CONFIG_FSL_QIXIS
 247 int checkboard(void)
 248 {
 249 #ifdef CONFIG_TFABOOT
 250         enum boot_src src = get_boot_src();
 251 #endif
 252         u8 sw;
 253
 254         int clock;
 255         char *board;
 256         char buf[64] = {0};
 257         static const char *freq[6] = {"100.00", "125.00", "156.25",
 258                                         "161.13", "322.26", "100.00 SS"};
 259
 260         cpu_name(buf);
 261         /* find the board details */
 262         sw = QIXIS_READ(id);
 263
 264         switch (sw) {
 265         case 0x46:
 266                 board = "QDS";
 267                 break;
 268         case 0x47:
 269                 board = "RDB";
 270                 break;
 271         case 0x49:
 272                 board = "HSSI";
 273                 break;
 274         default:
 275                 board = "unknown";
 276                 break;
 277         }
 278
 279         sw = QIXIS_READ(arch);
 280         printf("Board: %s-%s, Version: %c, boot from ",
 281                buf, board, (sw & 0xf) + 'A' - 1);
 282
 283         sw = QIXIS_READ(brdcfg[0]);
 284         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 285
 286 #ifdef CONFIG_TFABOOT
 287         if (src == BOOT_SOURCE_SD_MMC) {
 288                 puts("SD\n");
 289         } else if (src == BOOT_SOURCE_SD_MMC2) {
 290                 puts("eMMC\n");
 291         } else {
 292 #endif
 293 #ifdef CONFIG_SD_BOOT
 294                 puts("SD\n");
 295 #elif defined(CONFIG_EMMC_BOOT)
 296                 puts("eMMC\n");
 297 #else
 298                 switch (sw) {
 299                 case 0:
 300                 case 4:
 301                         printf("NOR\n");
 302                         break;
 303                 case 1:
 304                         printf("NAND\n");
 305                         break;
 306                 default:
 307                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 308                         break;
 309                 }
 310 #endif
 311 #ifdef CONFIG_TFABOOT
 312         }
 313 #endif
 314
 315         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 316         puts("SERDES1 Reference : ");
 317
 318         sw = QIXIS_READ(brdcfg[2]);
 319 #ifdef CONFIG_TARGET_LS1028ARDB
 320         clock = (sw >> 6) & 3;
 321 #else
 322         clock = (sw >> 4) & 0xf;
 323 #endif
 324
 325         printf("Clock1 = %sMHz ", freq[clock]);
 326 #ifdef CONFIG_TARGET_LS1028ARDB
 327         clock = (sw >> 4) & 3;
 328 #else
 329         clock = sw & 0xf;
 330 #endif
 331         printf("Clock2 = %sMHz\n", freq[clock]);
 332
 333         return 0;
 334 }
 335 #endif