board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019-2022 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <malloc.h>
   9 #include <errno.h>
  10 #include <fsl_ddr.h>
  11 #include <net.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <hwconfig.h>
  15 #include <fdt_support.h>
  16 #include <linux/libfdt.h>
  17 #include <env_internal.h>
  18 #include <asm/arch-fsl-layerscape/soc.h>
  19 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  20 #include <i2c.h>
  21 #include <asm/arch/soc.h>
  22 #ifdef CONFIG_FSL_LS_PPA
  23 #include <asm/arch/ppa.h>
  24 #endif
  25 #include <fsl_immap.h>
  26 #include <netdev.h>
  27
  28 #include <fdtdec.h>
  29 #include <miiphy.h>
  30 #include "../common/qixis.h"
  31 #include "../drivers/net/fsl_enetc.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 int config_board_mux(void)
  36 {
  37 #ifndef CONFIG_LPUART
  38 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  39         u8 reg;
  40
  41         reg = QIXIS_READ(brdcfg[13]);
  42         /* Field| Function
  43          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  44          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  45          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  46          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  47          */
  48         reg &= ~(0xf0);
  49         reg |= 0xb0;
  50         QIXIS_WRITE(brdcfg[13], reg);
  51
  52         reg = QIXIS_READ(brdcfg[15]);
  53         /* Field| Function
  54          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  55          * CAN1 | 0= CAN #1 transceiver enabled
  56          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  57          * CAN2 | 0= CAN #2 transceiver enabled
  58          */
  59         reg &= ~(0xc0);
  60         QIXIS_WRITE(brdcfg[15], reg);
  61 #endif
  62 #endif
  63
  64         return 0;
  65 }
  66
  67 #ifdef CONFIG_LPUART
  68 u32 get_lpuart_clk(void)
  69 {
  70         return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
  71 }
  72 #endif
  73
  74 int board_init(void)
  75 {
  76 #ifdef CONFIG_FSL_LS_PPA
  77         ppa_init();
  78 #endif
  79
  80 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  81         pci_init();
  82 #endif
  83
  84 #if defined(CONFIG_TARGET_LS1028ARDB)
  85         u8 val = I2C_MUX_CH_DEFAULT;
  86
  87 #if !CONFIG_IS_ENABLED(DM_I2C)
  88         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  89 #else
  90         struct udevice *dev;
  91
  92         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  93                 dm_i2c_write(dev, 0x0b, &val, 1);
  94 #endif
  95 #endif
  96
  97 #if defined(CONFIG_TARGET_LS1028ARDB)
  98         u8 reg;
  99
 100         reg = QIXIS_READ(brdcfg[4]);
 101         /*
 102          * Field | Function
 103          * 3     | DisplayPort Power Enable (net DP_PWR_EN):
 104          * DPPWR | 0= DP_PWR is enabled.
 105          */
 106         reg &= ~(DP_PWD_EN_DEFAULT_MASK);
 107         QIXIS_WRITE(brdcfg[4], reg);
 108 #endif
 109         return 0;
 110 }
 111
 112 int board_eth_init(struct bd_info *bis)
 113 {
 114         return pci_eth_init(bis);
 115 }
 116
 117 #ifdef CONFIG_MISC_INIT_R
 118 int misc_init_r(void)
 119 {
 120         config_board_mux();
 121
 122         return 0;
 123 }
 124 #endif
 125
 126 int board_early_init_f(void)
 127 {
 128 #ifdef CONFIG_LPUART
 129         u8 uart;
 130 #endif
 131
 132 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
 133         i2c_early_init_f();
 134 #endif
 135
 136         fsl_lsch3_early_init_f();
 137
 138 #ifdef CONFIG_LPUART
 139         /*
 140          * Field| Function
 141          * --------------------------------------------------------------
 142          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
 143          * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
 144          * --------------------------------------------------------------
 145          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
 146          * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
 147          */
 148         /* use lpuart0 as system console */
 149         uart = QIXIS_READ(brdcfg[13]);
 150         uart &= ~CFG_LPUART_MUX_MASK;
 151         uart |= CFG_LPUART_EN;
 152         QIXIS_WRITE(brdcfg[13], uart);
 153 #endif
 154
 155         return 0;
 156 }
 157
 158 void detail_board_ddr_info(void)
 159 {
 160         puts("\nDDR    ");
 161         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 162         print_ddr_info(0);
 163 }
 164
 165 int esdhc_status_fixup(void *blob, const char *compat)
 166 {
 167         void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
 168         char esdhc1_path[] = "/soc/mmc@2140000";
 169         char esdhc2_path[] = "/soc/mmc@2150000";
 170         char dspi1_path[] = "/soc/spi@2100000";
 171         char dspi2_path[] = "/soc/spi@2110000";
 172         u32 mux_sdhc1, mux_sdhc2;
 173         u32 io = 0;
 174
 175         /*
 176          * The PMUX IO-expander for mux select is used to control
 177          * the muxing of various onboard interfaces.
 178          */
 179
 180         io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
 181         mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
 182
 183         /* Disable esdhc1/dspi1 if not selected. */
 184         if (mux_sdhc1 != 0)
 185                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 186                                  sizeof("disabled"), 1);
 187         if (mux_sdhc1 != 2)
 188                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 189                                  sizeof("disabled"), 1);
 190
 191         io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
 192         mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
 193
 194         /* Disable esdhc2/dspi2 if not selected. */
 195         if (mux_sdhc2 != 0)
 196                 do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
 197                                  sizeof("disabled"), 1);
 198         if (mux_sdhc2 != 2)
 199                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 200                                  sizeof("disabled"), 1);
 201
 202         return 0;
 203 }
 204
 205 #ifdef CONFIG_OF_BOARD_SETUP
 206 int ft_board_setup(void *blob, struct bd_info *bd)
 207 {
 208         u64 base[CONFIG_NR_DRAM_BANKS];
 209         u64 size[CONFIG_NR_DRAM_BANKS];
 210
 211         ft_cpu_setup(blob, bd);
 212
 213         /* fixup DT for the two GPP DDR banks */
 214         base[0] = gd->bd->bi_dram[0].start;
 215         size[0] = gd->bd->bi_dram[0].size;
 216         base[1] = gd->bd->bi_dram[1].start;
 217         size[1] = gd->bd->bi_dram[1].size;
 218
 219 #ifdef CONFIG_RESV_RAM
 220         /* reduce size if reserved memory is within this bank */
 221         if (gd->arch.resv_ram >= base[0] &&
 222             gd->arch.resv_ram < base[0] + size[0])
 223                 size[0] = gd->arch.resv_ram - base[0];
 224         else if (gd->arch.resv_ram >= base[1] &&
 225                  gd->arch.resv_ram < base[1] + size[1])
 226                 size[1] = gd->arch.resv_ram - base[1];
 227 #endif
 228
 229         fdt_fixup_memory_banks(blob, base, size, 2);
 230
 231         fdt_fixup_icid(blob);
 232
 233 #ifdef CONFIG_FSL_ENETC
 234         fdt_fixup_enetc_mac(blob);
 235 #endif
 236
 237         return 0;
 238 }
 239 #endif
 240
 241 #ifdef CONFIG_FSL_QIXIS
 242 int checkboard(void)
 243 {
 244 #ifdef CONFIG_TFABOOT
 245         enum boot_src src = get_boot_src();
 246 #endif
 247         u8 sw;
 248
 249         int clock;
 250         char *board;
 251         char buf[64] = {0};
 252         static const char *freq[6] = {"100.00", "125.00", "156.25",
 253                                         "161.13", "322.26", "100.00 SS"};
 254
 255         cpu_name(buf);
 256         /* find the board details */
 257         sw = QIXIS_READ(id);
 258
 259         switch (sw) {
 260         case 0x46:
 261                 board = "QDS";
 262                 break;
 263         case 0x47:
 264                 board = "RDB";
 265                 break;
 266         case 0x49:
 267                 board = "HSSI";
 268                 break;
 269         default:
 270                 board = "unknown";
 271                 break;
 272         }
 273
 274         sw = QIXIS_READ(arch);
 275         printf("Board: %s-%s, Version: %c, boot from ",
 276                buf, board, (sw & 0xf) + 'A' - 1);
 277
 278         sw = QIXIS_READ(brdcfg[0]);
 279         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 280
 281 #ifdef CONFIG_TFABOOT
 282         if (src == BOOT_SOURCE_SD_MMC) {
 283                 puts("SD\n");
 284         } else if (src == BOOT_SOURCE_SD_MMC2) {
 285                 puts("eMMC\n");
 286         } else {
 287 #endif
 288 #ifdef CONFIG_SD_BOOT
 289                 puts("SD\n");
 290 #elif defined(CONFIG_EMMC_BOOT)
 291                 puts("eMMC\n");
 292 #else
 293                 switch (sw) {
 294                 case 0:
 295                 case 4:
 296                         printf("NOR\n");
 297                         break;
 298                 case 1:
 299                         printf("NAND\n");
 300                         break;
 301                 default:
 302                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 303                         break;
 304                 }
 305 #endif
 306 #ifdef CONFIG_TFABOOT
 307         }
 308 #endif
 309
 310         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 311         puts("SERDES1 Reference : ");
 312
 313         sw = QIXIS_READ(brdcfg[2]);
 314 #ifdef CONFIG_TARGET_LS1028ARDB
 315         clock = (sw >> 6) & 3;
 316 #else
 317         clock = (sw >> 4) & 0xf;
 318 #endif
 319
 320         printf("Clock1 = %sMHz ", freq[clock]);
 321 #ifdef CONFIG_TARGET_LS1028ARDB
 322         clock = (sw >> 4) & 3;
 323 #else
 324         clock = sw & 0xf;
 325 #endif
 326         printf("Clock2 = %sMHz\n", freq[clock]);
 327
 328         return 0;
 329 }
 330 #endif
 331
 332 void *video_hw_init(void)
 333 {
 334         return NULL;
 335 }