board/freescale/ls1028a/ls1028a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <errno.h>
   9 #include <fsl_ddr.h>
  10 #include <asm/io.h>
  11 #include <hwconfig.h>
  12 #include <fdt_support.h>
  13 #include <linux/libfdt.h>
  14 #include <env_internal.h>
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  17 #include <i2c.h>
  18 #include <asm/arch/soc.h>
  19 #ifdef CONFIG_FSL_LS_PPA
  20 #include <asm/arch/ppa.h>
  21 #endif
  22 #include <fsl_immap.h>
  23 #include <netdev.h>
  24
  25 #include <fdtdec.h>
  26 #include <miiphy.h>
  27 #include "../common/qixis.h"
  28 #include "../drivers/net/fsl_enetc.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 int config_board_mux(void)
  33 {
  34 #if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
  35         u8 reg;
  36
  37         reg = QIXIS_READ(brdcfg[13]);
  38         /* Field| Function
  39          * 7-6  | Controls I2C3 routing (net CFG_MUX_I2C3):
  40          * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
  41          * 5-4  | Controls I2C4 routing (net CFG_MUX_I2C4):
  42          * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
  43          */
  44         reg &= ~(0xf0);
  45         reg |= 0xb0;
  46         QIXIS_WRITE(brdcfg[13], reg);
  47
  48         reg = QIXIS_READ(brdcfg[15]);
  49         /* Field| Function
  50          * 7    | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
  51          * CAN1 | 0= CAN #1 transceiver enabled
  52          * 6    | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
  53          * CAN2 | 0= CAN #2 transceiver enabled
  54          */
  55         reg &= ~(0xc0);
  56         QIXIS_WRITE(brdcfg[15], reg);
  57 #endif
  58         return 0;
  59 }
  60
  61 int board_init(void)
  62 {
  63 #ifdef CONFIG_ENV_IS_NOWHERE
  64         gd->env_addr = (ulong)&default_environment[0];
  65 #endif
  66
  67 #ifdef CONFIG_FSL_CAAM
  68         sec_init();
  69 #endif
  70
  71 #ifdef CONFIG_FSL_LS_PPA
  72         ppa_init();
  73 #endif
  74
  75 #ifndef CONFIG_SYS_EARLY_PCI_INIT
  76         pci_init();
  77 #endif
  78
  79 #if defined(CONFIG_TARGET_LS1028ARDB)
  80         u8 val = I2C_MUX_CH_DEFAULT;
  81
  82 #ifndef CONFIG_DM_I2C
  83         i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
  84 #else
  85         struct udevice *dev;
  86
  87         if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
  88                 dm_i2c_write(dev, 0x0b, &val, 1);
  89 #endif
  90 #endif
  91
  92 #if defined(CONFIG_TARGET_LS1028ARDB)
  93         u8 reg;
  94
  95         reg = QIXIS_READ(brdcfg[4]);
  96         /*
  97          * Field | Function
  98          * 3     | DisplayPort Power Enable (net DP_PWR_EN):
  99          * DPPWR | 0= DP_PWR is enabled.
 100          */
 101         reg &= ~(DP_PWD_EN_DEFAULT_MASK);
 102         QIXIS_WRITE(brdcfg[4], reg);
 103 #endif
 104         return 0;
 105 }
 106
 107 int board_eth_init(bd_t *bis)
 108 {
 109         return pci_eth_init(bis);
 110 }
 111
 112 #ifdef CONFIG_MISC_INIT_R
 113 int misc_init_r(void)
 114 {
 115         config_board_mux();
 116
 117         return 0;
 118 }
 119 #endif
 120
 121 int board_early_init_f(void)
 122 {
 123 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 124         i2c_early_init_f();
 125 #endif
 126
 127         fsl_lsch3_early_init_f();
 128         return 0;
 129 }
 130
 131 void detail_board_ddr_info(void)
 132 {
 133         puts("\nDDR    ");
 134         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 135         print_ddr_info(0);
 136 }
 137
 138 int esdhc_status_fixup(void *blob, const char *compat)
 139 {
 140         void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
 141         char esdhc1_path[] = "/soc/mmc@2140000";
 142         char esdhc2_path[] = "/soc/mmc@2150000";
 143         char dspi1_path[] = "/soc/spi@2100000";
 144         char dspi2_path[] = "/soc/spi@2110000";
 145         u32 mux_sdhc1, mux_sdhc2;
 146         u32 io = 0;
 147
 148         /*
 149          * The PMUX IO-expander for mux select is used to control
 150          * the muxing of various onboard interfaces.
 151          */
 152
 153         io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
 154         mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
 155
 156         /* Disable esdhc1/dspi1 if not selected. */
 157         if (mux_sdhc1 != 0)
 158                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 159                                  sizeof("disabled"), 1);
 160         if (mux_sdhc1 != 2)
 161                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 162                                  sizeof("disabled"), 1);
 163
 164         io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
 165         mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
 166
 167         /* Disable esdhc2/dspi2 if not selected. */
 168         if (mux_sdhc2 != 0)
 169                 do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
 170                                  sizeof("disabled"), 1);
 171         if (mux_sdhc2 != 2)
 172                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 173                                  sizeof("disabled"), 1);
 174
 175         return 0;
 176 }
 177
 178 #ifdef CONFIG_OF_BOARD_SETUP
 179 int ft_board_setup(void *blob, bd_t *bd)
 180 {
 181         u64 base[CONFIG_NR_DRAM_BANKS];
 182         u64 size[CONFIG_NR_DRAM_BANKS];
 183
 184         ft_cpu_setup(blob, bd);
 185
 186         /* fixup DT for the two GPP DDR banks */
 187         base[0] = gd->bd->bi_dram[0].start;
 188         size[0] = gd->bd->bi_dram[0].size;
 189         base[1] = gd->bd->bi_dram[1].start;
 190         size[1] = gd->bd->bi_dram[1].size;
 191
 192 #ifdef CONFIG_RESV_RAM
 193         /* reduce size if reserved memory is within this bank */
 194         if (gd->arch.resv_ram >= base[0] &&
 195             gd->arch.resv_ram < base[0] + size[0])
 196                 size[0] = gd->arch.resv_ram - base[0];
 197         else if (gd->arch.resv_ram >= base[1] &&
 198                  gd->arch.resv_ram < base[1] + size[1])
 199                 size[1] = gd->arch.resv_ram - base[1];
 200 #endif
 201
 202         fdt_fixup_memory_banks(blob, base, size, 2);
 203
 204         fdt_fixup_icid(blob);
 205
 206 #ifdef CONFIG_FSL_ENETC
 207         fdt_fixup_enetc_mac(blob);
 208 #endif
 209
 210         return 0;
 211 }
 212 #endif
 213
 214 #ifdef CONFIG_FSL_QIXIS
 215 int checkboard(void)
 216 {
 217 #ifdef CONFIG_TFABOOT
 218         enum boot_src src = get_boot_src();
 219 #endif
 220         u8 sw;
 221
 222         int clock;
 223         char *board;
 224         char buf[64] = {0};
 225         static const char *freq[6] = {"100.00", "125.00", "156.25",
 226                                         "161.13", "322.26", "100.00 SS"};
 227
 228         cpu_name(buf);
 229         /* find the board details */
 230         sw = QIXIS_READ(id);
 231
 232         switch (sw) {
 233         case 0x46:
 234                 board = "QDS";
 235                 break;
 236         case 0x47:
 237                 board = "RDB";
 238                 break;
 239         case 0x49:
 240                 board = "HSSI";
 241                 break;
 242         default:
 243                 board = "unknown";
 244                 break;
 245         }
 246
 247         sw = QIXIS_READ(arch);
 248         printf("Board: %s-%s, Version: %c, boot from ",
 249                buf, board, (sw & 0xf) + 'A' - 1);
 250
 251         sw = QIXIS_READ(brdcfg[0]);
 252         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 253
 254 #ifdef CONFIG_TFABOOT
 255         if (src == BOOT_SOURCE_SD_MMC) {
 256                 puts("SD\n");
 257         } else if (src == BOOT_SOURCE_SD_MMC2) {
 258                 puts("eMMC\n");
 259         } else {
 260 #endif
 261 #ifdef CONFIG_SD_BOOT
 262                 puts("SD\n");
 263 #elif defined(CONFIG_EMMC_BOOT)
 264                 puts("eMMC\n");
 265 #else
 266                 switch (sw) {
 267                 case 0:
 268                 case 4:
 269                         printf("NOR\n");
 270                         break;
 271                 case 1:
 272                         printf("NAND\n");
 273                         break;
 274                 default:
 275                         printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 276                         break;
 277                 }
 278 #endif
 279 #ifdef CONFIG_TFABOOT
 280         }
 281 #endif
 282
 283         printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
 284         puts("SERDES1 Reference : ");
 285
 286         sw = QIXIS_READ(brdcfg[2]);
 287 #ifdef CONFIG_TARGET_LS1028ARDB
 288         clock = (sw >> 6) & 3;
 289 #else
 290         clock = (sw >> 4) & 0xf;
 291 #endif
 292
 293         printf("Clock1 = %sMHz ", freq[clock]);
 294 #ifdef CONFIG_TARGET_LS1028ARDB
 295         clock = (sw >> 4) & 3;
 296 #else
 297         clock = sw & 0xf;
 298 #endif
 299         printf("Clock2 = %sMHz\n", freq[clock]);
 300
 301         return 0;
 302 }
 303 #endif