Merge git://git.denx.de/u-boot-rockchip
[platform/kernel/u-boot.git] / board / freescale / ls1021atwr / ls1021atwr.c
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ns_access.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ls102xa_stream_id.h>
15 #include <asm/arch/ls102xa_devdis.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <fsl_esdhc.h>
19 #include <fsl_ifc.h>
20 #include <fsl_immap.h>
21 #include <netdev.h>
22 #include <fsl_mdio.h>
23 #include <tsec.h>
24 #include <fsl_sec.h>
25 #include <fsl_devdis.h>
26 #include <spl.h>
27 #include "../common/sleep.h"
28 #ifdef CONFIG_U_QE
29 #include "../../../drivers/qe/qe.h"
30 #endif
31
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define VERSION_MASK            0x00FF
36 #define BANK_MASK               0x0001
37 #define CONFIG_RESET            0x1
38 #define INIT_RESET              0x1
39
40 #define CPLD_SET_MUX_SERDES     0x20
41 #define CPLD_SET_BOOT_BANK      0x40
42
43 #define BOOT_FROM_UPPER_BANK    0x0
44 #define BOOT_FROM_LOWER_BANK    0x1
45
46 #define LANEB_SATA              (0x01)
47 #define LANEB_SGMII1            (0x02)
48 #define LANEC_SGMII1            (0x04)
49 #define LANEC_PCIEX1            (0x08)
50 #define LANED_PCIEX2            (0x10)
51 #define LANED_SGMII2            (0x20)
52
53 #define MASK_LANE_B             0x1
54 #define MASK_LANE_C             0x2
55 #define MASK_LANE_D             0x4
56 #define MASK_SGMII              0x8
57
58 #define KEEP_STATUS             0x0
59 #define NEED_RESET              0x1
60
61 #define SOFT_MUX_ON_I2C3_IFC    0x2
62 #define SOFT_MUX_ON_CAN3_USB2   0x8
63 #define SOFT_MUX_ON_QE_LCD      0x10
64
65 #define PIN_I2C3_IFC_MUX_I2C3   0x0
66 #define PIN_I2C3_IFC_MUX_IFC    0x1
67 #define PIN_CAN3_USB2_MUX_USB2  0x0
68 #define PIN_CAN3_USB2_MUX_CAN3  0x1
69 #define PIN_QE_LCD_MUX_LCD      0x0
70 #define PIN_QE_LCD_MUX_QE       0x1
71
72 #ifdef CONFIG_LS102XA_NS_ACCESS
73 static struct csu_ns_dev ns_dev[] = {
74         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
75         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
76         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
77         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
78         { CSU_CSLX_OCRAM, CSU_ALL_RW },
79         { CSU_CSLX_GIC, CSU_ALL_RW },
80         { CSU_CSLX_PCIE1, CSU_ALL_RW },
81         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
82         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
83         { CSU_CSLX_PCIE2, CSU_ALL_RW },
84         { CSU_CSLX_SATA, CSU_ALL_RW },
85         { CSU_CSLX_USB3, CSU_ALL_RW },
86         { CSU_CSLX_SERDES, CSU_ALL_RW },
87         { CSU_CSLX_QDMA, CSU_ALL_RW },
88         { CSU_CSLX_LPUART2, CSU_ALL_RW },
89         { CSU_CSLX_LPUART1, CSU_ALL_RW },
90         { CSU_CSLX_LPUART4, CSU_ALL_RW },
91         { CSU_CSLX_LPUART3, CSU_ALL_RW },
92         { CSU_CSLX_LPUART6, CSU_ALL_RW },
93         { CSU_CSLX_LPUART5, CSU_ALL_RW },
94         { CSU_CSLX_DSPI2, CSU_ALL_RW },
95         { CSU_CSLX_DSPI1, CSU_ALL_RW },
96         { CSU_CSLX_QSPI, CSU_ALL_RW },
97         { CSU_CSLX_ESDHC, CSU_ALL_RW },
98         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
99         { CSU_CSLX_IFC, CSU_ALL_RW },
100         { CSU_CSLX_I2C1, CSU_ALL_RW },
101         { CSU_CSLX_USB2, CSU_ALL_RW },
102         { CSU_CSLX_I2C3, CSU_ALL_RW },
103         { CSU_CSLX_I2C2, CSU_ALL_RW },
104         { CSU_CSLX_DUART2, CSU_ALL_RW },
105         { CSU_CSLX_DUART1, CSU_ALL_RW },
106         { CSU_CSLX_WDT2, CSU_ALL_RW },
107         { CSU_CSLX_WDT1, CSU_ALL_RW },
108         { CSU_CSLX_EDMA, CSU_ALL_RW },
109         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
110         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
111         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
112         { CSU_CSLX_DDR, CSU_ALL_RW },
113         { CSU_CSLX_QUICC, CSU_ALL_RW },
114         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
115         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
116         { CSU_CSLX_SFP, CSU_ALL_RW },
117         { CSU_CSLX_TMU, CSU_ALL_RW },
118         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
119         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
120         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
121         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
122         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
123         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
124         { CSU_CSLX_GPIO2, CSU_ALL_RW },
125         { CSU_CSLX_GPIO1, CSU_ALL_RW },
126         { CSU_CSLX_GPIO4, CSU_ALL_RW },
127         { CSU_CSLX_GPIO3, CSU_ALL_RW },
128         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
129         { CSU_CSLX_CSU, CSU_ALL_RW },
130         { CSU_CSLX_ASRC, CSU_ALL_RW },
131         { CSU_CSLX_SPDIF, CSU_ALL_RW },
132         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
133         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
134         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
135         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
136         { CSU_CSLX_SAI2, CSU_ALL_RW },
137         { CSU_CSLX_SAI1, CSU_ALL_RW },
138         { CSU_CSLX_SAI4, CSU_ALL_RW },
139         { CSU_CSLX_SAI3, CSU_ALL_RW },
140         { CSU_CSLX_FTM2, CSU_ALL_RW },
141         { CSU_CSLX_FTM1, CSU_ALL_RW },
142         { CSU_CSLX_FTM4, CSU_ALL_RW },
143         { CSU_CSLX_FTM3, CSU_ALL_RW },
144         { CSU_CSLX_FTM6, CSU_ALL_RW },
145         { CSU_CSLX_FTM5, CSU_ALL_RW },
146         { CSU_CSLX_FTM8, CSU_ALL_RW },
147         { CSU_CSLX_FTM7, CSU_ALL_RW },
148         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
149         { CSU_CSLX_EPU, CSU_ALL_RW },
150         { CSU_CSLX_GDI, CSU_ALL_RW },
151         { CSU_CSLX_DDI, CSU_ALL_RW },
152         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
153         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
154         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
155 };
156 #endif
157
158 struct cpld_data {
159         u8 cpld_ver;            /* cpld revision */
160         u8 cpld_ver_sub;        /* cpld sub revision */
161         u8 pcba_ver;            /* pcb revision number */
162         u8 system_rst;          /* reset system by cpld */
163         u8 soft_mux_on;         /* CPLD override physical switches Enable */
164         u8 cfg_rcw_src1;        /* Reset config word 1 */
165         u8 cfg_rcw_src2;        /* Reset config word 2 */
166         u8 vbank;               /* Flash bank selection Control */
167         u8 gpio;                /* GPIO for TWR-ELEV */
168         u8 i2c3_ifc_mux;
169         u8 mux_spi2;
170         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
171         u8 qe_lcd_mux;          /* QE and LCD Selection */
172         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
173         u8 global_rst;          /* reset with init CPLD reg to default */
174         u8 rev1;                /* Reserved */
175         u8 rev2;                /* Reserved */
176 };
177
178 #ifndef CONFIG_QSPI_BOOT
179 static void convert_serdes_mux(int type, int need_reset);
180
181 void cpld_show(void)
182 {
183         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
184
185         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
186                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
187                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
188                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
189                in_8(&cpld_data->vbank) & BANK_MASK);
190
191 #ifdef CONFIG_DEBUG
192         printf("soft_mux_on =%x\n",
193                in_8(&cpld_data->soft_mux_on));
194         printf("cfg_rcw_src1 =%x\n",
195                in_8(&cpld_data->cfg_rcw_src1));
196         printf("cfg_rcw_src2 =%x\n",
197                in_8(&cpld_data->cfg_rcw_src2));
198         printf("vbank =%x\n",
199                in_8(&cpld_data->vbank));
200         printf("gpio =%x\n",
201                in_8(&cpld_data->gpio));
202         printf("i2c3_ifc_mux =%x\n",
203                in_8(&cpld_data->i2c3_ifc_mux));
204         printf("mux_spi2 =%x\n",
205                in_8(&cpld_data->mux_spi2));
206         printf("can3_usb2_mux =%x\n",
207                in_8(&cpld_data->can3_usb2_mux));
208         printf("qe_lcd_mux =%x\n",
209                in_8(&cpld_data->qe_lcd_mux));
210         printf("serdes_mux =%x\n",
211                in_8(&cpld_data->serdes_mux));
212 #endif
213 }
214 #endif
215
216 int checkboard(void)
217 {
218         puts("Board: LS1021ATWR\n");
219 #ifndef CONFIG_QSPI_BOOT
220         cpld_show();
221 #endif
222
223         return 0;
224 }
225
226 unsigned int get_soc_major_rev(void)
227 {
228         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
229         unsigned int svr, major;
230
231         svr = in_be32(&gur->svr);
232         major = SVR_MAJ(svr);
233
234         return major;
235 }
236
237 void ddrmc_init(void)
238 {
239         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
240         u32 temp_sdram_cfg;
241
242         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
243
244         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
245         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
246
247         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
248         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
249         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
250         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
251         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
252         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
253
254 #ifdef CONFIG_DEEP_SLEEP
255         if (is_warm_boot()) {
256                 out_be32(&ddr->sdram_cfg_2,
257                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
258                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
259                 out_be32(&ddr->init_ext_addr, (1 << 31));
260
261                 /* DRAM VRef will not be trained */
262                 out_be32(&ddr->ddr_cdr2,
263                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
264         } else
265 #endif
266         {
267                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
268                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
269         }
270
271         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
272         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
273
274         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
275
276         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
277
278         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
279         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
280
281         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
282
283         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
284         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
285
286         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
287         udelay(1);
288
289 #ifdef CONFIG_DEEP_SLEEP
290         if (is_warm_boot()) {
291                 /* enter self-refresh */
292                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
293                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
294                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
295
296                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
297         } else
298 #endif
299                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
300
301         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
302
303 #ifdef CONFIG_DEEP_SLEEP
304         if (is_warm_boot()) {
305                 /* exit self-refresh */
306                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
307                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
308                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
309         }
310 #endif
311 }
312
313 int dram_init(void)
314 {
315 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
316         ddrmc_init();
317 #endif
318
319         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
320
321 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
322         fsl_dp_resume();
323 #endif
324
325         return 0;
326 }
327
328 #ifdef CONFIG_FSL_ESDHC
329 struct fsl_esdhc_cfg esdhc_cfg[1] = {
330         {CONFIG_SYS_FSL_ESDHC_ADDR},
331 };
332
333 int board_mmc_init(bd_t *bis)
334 {
335         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
336
337         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
338 }
339 #endif
340
341 #ifdef CONFIG_TSEC_ENET
342 int board_eth_init(bd_t *bis)
343 {
344         struct fsl_pq_mdio_info mdio_info;
345         struct tsec_info_struct tsec_info[4];
346         int num = 0;
347
348 #ifdef CONFIG_TSEC1
349         SET_STD_TSEC_INFO(tsec_info[num], 1);
350         if (is_serdes_configured(SGMII_TSEC1)) {
351                 puts("eTSEC1 is in sgmii mode.\n");
352                 tsec_info[num].flags |= TSEC_SGMII;
353         }
354         num++;
355 #endif
356 #ifdef CONFIG_TSEC2
357         SET_STD_TSEC_INFO(tsec_info[num], 2);
358         if (is_serdes_configured(SGMII_TSEC2)) {
359                 puts("eTSEC2 is in sgmii mode.\n");
360                 tsec_info[num].flags |= TSEC_SGMII;
361         }
362         num++;
363 #endif
364 #ifdef CONFIG_TSEC3
365         SET_STD_TSEC_INFO(tsec_info[num], 3);
366         num++;
367 #endif
368         if (!num) {
369                 printf("No TSECs initialized\n");
370                 return 0;
371         }
372
373         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
374         mdio_info.name = DEFAULT_MII_NAME;
375         fsl_pq_mdio_init(bis, &mdio_info);
376
377         tsec_eth_init(bis, tsec_info, num);
378
379         return pci_eth_init(bis);
380 }
381 #endif
382
383 #ifndef CONFIG_QSPI_BOOT
384 int config_serdes_mux(void)
385 {
386         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
387         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
388
389         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
390         switch (protocol) {
391         case 0x10:
392                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
393                 convert_serdes_mux(LANED_PCIEX2 |
394                                 LANEC_PCIEX1, KEEP_STATUS);
395                 break;
396         case 0x20:
397                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
398                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
399                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
400                 break;
401         case 0x30:
402                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
403                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
404                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
405                 break;
406         case 0x70:
407                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
408                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
409                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
410                 break;
411         }
412
413         return 0;
414 }
415 #endif
416
417 #ifndef CONFIG_QSPI_BOOT
418 int config_board_mux(void)
419 {
420         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
421         int conflict_flag;
422
423         conflict_flag = 0;
424         if (hwconfig("i2c3")) {
425                 conflict_flag++;
426                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
427                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
428         }
429
430         if (hwconfig("ifc")) {
431                 conflict_flag++;
432                 /* some signals can not enable simultaneous*/
433                 if (conflict_flag > 1)
434                         goto conflict;
435                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
436                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
437         }
438
439         conflict_flag = 0;
440         if (hwconfig("usb2")) {
441                 conflict_flag++;
442                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
443                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
444         }
445
446         if (hwconfig("can3")) {
447                 conflict_flag++;
448                 /* some signals can not enable simultaneous*/
449                 if (conflict_flag > 1)
450                         goto conflict;
451                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
452                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
453         }
454
455         conflict_flag = 0;
456         if (hwconfig("lcd")) {
457                 conflict_flag++;
458                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
459                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
460         }
461
462         if (hwconfig("qe")) {
463                 conflict_flag++;
464                 /* some signals can not enable simultaneous*/
465                 if (conflict_flag > 1)
466                         goto conflict;
467                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
468                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
469         }
470
471         return 0;
472
473 conflict:
474         printf("WARNING: pin conflict! MUX setting may failed!\n");
475         return 0;
476 }
477 #endif
478
479 int board_early_init_f(void)
480 {
481         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
482         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
483         unsigned int major;
484
485 #ifdef CONFIG_TSEC_ENET
486         /* clear BD & FR bits for BE BD's and frame data */
487         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
488         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
489 #endif
490
491 #ifdef CONFIG_FSL_IFC
492         init_early_memctl_regs();
493 #endif
494
495 #ifdef CONFIG_FSL_DCU_FB
496         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
497 #endif
498
499 #ifdef CONFIG_FSL_QSPI
500         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
501 #endif
502
503         /* Configure Little endian for SAI, ASRC and SPDIF */
504         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
505
506         /*
507          * Enable snoop requests and DVM message requests for
508          * Slave insterface S4 (A7 core cluster)
509          */
510         out_le32(&cci->slave[4].snoop_ctrl,
511                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
512
513         major = get_soc_major_rev();
514         if (major == SOC_MAJOR_VER_1_0) {
515                 /*
516                  * Set CCI-400 Slave interface S1, S2 Shareable Override
517                  * Register All transactions are treated as non-shareable
518                  */
519                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
520                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
521         }
522
523 #if defined(CONFIG_DEEP_SLEEP)
524         if (is_warm_boot())
525                 fsl_dp_disable_console();
526 #endif
527
528         return 0;
529 }
530
531 #ifdef CONFIG_SPL_BUILD
532 void board_init_f(ulong dummy)
533 {
534         /* Clear the BSS */
535         memset(__bss_start, 0, __bss_end - __bss_start);
536
537         get_clocks();
538
539 #if defined(CONFIG_DEEP_SLEEP)
540         if (is_warm_boot())
541                 fsl_dp_disable_console();
542 #endif
543
544         preloader_console_init();
545
546         dram_init();
547
548         /* Allow OCRAM access permission as R/W */
549 #ifdef CONFIG_LS102XA_NS_ACCESS
550         enable_devices_ns_access(&ns_dev[4], 1);
551         enable_devices_ns_access(&ns_dev[7], 1);
552 #endif
553
554         board_init_r(NULL, 0);
555 }
556 #endif
557
558
559 struct liodn_id_table sec_liodn_tbl[] = {
560         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
561         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
562         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
563         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
564         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
565         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
566         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
567         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
568         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
569         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
570         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
571         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
572         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
573         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
574         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
575         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
576 };
577
578 struct smmu_stream_id dev_stream_id[] = {
579         { 0x100, 0x01, "ETSEC MAC1" },
580         { 0x104, 0x02, "ETSEC MAC2" },
581         { 0x108, 0x03, "ETSEC MAC3" },
582         { 0x10c, 0x04, "PEX1" },
583         { 0x110, 0x05, "PEX2" },
584         { 0x114, 0x06, "qDMA" },
585         { 0x118, 0x07, "SATA" },
586         { 0x11c, 0x08, "USB3" },
587         { 0x120, 0x09, "QE" },
588         { 0x124, 0x0a, "eSDHC" },
589         { 0x128, 0x0b, "eMA" },
590         { 0x14c, 0x0c, "2D-ACE" },
591         { 0x150, 0x0d, "USB2" },
592         { 0x18c, 0x0e, "DEBUG" },
593 };
594
595 #ifdef CONFIG_DEEP_SLEEP
596 /* program the regulator (MC34VR500) to support deep sleep */
597 void ls1twr_program_regulator(void)
598 {
599         unsigned int i2c_bus;
600         u8 i2c_device_id;
601
602 #define LS1TWR_I2C_BUS_MC34VR500        1
603 #define MC34VR500_ADDR                  0x8
604 #define MC34VR500_DEVICEID              0x4
605 #define MC34VR500_DEVICEID_MASK         0x0f
606
607         i2c_bus = i2c_get_bus_num();
608         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
609         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
610                                         MC34VR500_DEVICEID_MASK;
611         if (i2c_device_id != MC34VR500_DEVICEID) {
612                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
613                 return;
614         }
615
616         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
617         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
618         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
619         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
620         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
621
622         i2c_set_bus_num(i2c_bus);
623 }
624 #endif
625
626 int board_init(void)
627 {
628 #ifndef CONFIG_SYS_FSL_NO_SERDES
629         fsl_serdes_init();
630 #ifndef CONFIG_QSPI_BOOT
631         config_serdes_mux();
632 #endif
633 #endif
634
635         ls1021x_config_caam_stream_id(sec_liodn_tbl,
636                                       ARRAY_SIZE(sec_liodn_tbl));
637         ls102xa_config_smmu_stream_id(dev_stream_id,
638                                       ARRAY_SIZE(dev_stream_id));
639
640 #ifdef CONFIG_LS102XA_NS_ACCESS
641         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
642 #endif
643
644 #ifdef CONFIG_U_QE
645         u_qe_init();
646 #endif
647
648 #ifdef CONFIG_DEEP_SLEEP
649         ls1twr_program_regulator();
650 #endif
651         return 0;
652 }
653
654 #if defined(CONFIG_MISC_INIT_R)
655 int misc_init_r(void)
656 {
657 #ifdef CONFIG_FSL_DEVICE_DISABLE
658         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
659 #endif
660 #ifndef CONFIG_QSPI_BOOT
661         config_board_mux();
662 #endif
663
664 #ifdef CONFIG_FSL_CAAM
665         return sec_init();
666 #endif
667 }
668 #endif
669
670 #if defined(CONFIG_DEEP_SLEEP)
671 void board_sleep_prepare(void)
672 {
673 #ifdef CONFIG_LS102XA_NS_ACCESS
674         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
675 #endif
676 }
677 #endif
678
679 int ft_board_setup(void *blob, bd_t *bd)
680 {
681         ft_cpu_setup(blob, bd);
682
683 #ifdef CONFIG_PCI
684         ft_pci_setup(blob, bd);
685 #endif
686
687         return 0;
688 }
689
690 u8 flash_read8(void *addr)
691 {
692         return __raw_readb(addr + 1);
693 }
694
695 void flash_write16(u16 val, void *addr)
696 {
697         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
698
699         __raw_writew(shftval, addr);
700 }
701
702 u16 flash_read16(void *addr)
703 {
704         u16 val = __raw_readw(addr);
705
706         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
707 }
708
709 #ifndef CONFIG_QSPI_BOOT
710 static void convert_flash_bank(char bank)
711 {
712         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
713
714         printf("Now switch to boot from flash bank %d.\n", bank);
715         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
716         cpld_data->vbank = bank;
717
718         printf("Reset board to enable configuration.\n");
719         cpld_data->system_rst = CONFIG_RESET;
720 }
721
722 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
723                           char * const argv[])
724 {
725         if (argc != 2)
726                 return CMD_RET_USAGE;
727         if (strcmp(argv[1], "0") == 0)
728                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
729         else if (strcmp(argv[1], "1") == 0)
730                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
731         else
732                 return CMD_RET_USAGE;
733
734         return 0;
735 }
736
737 U_BOOT_CMD(
738         boot_bank, 2, 0, flash_bank_cmd,
739         "Flash bank Selection Control",
740         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
741 );
742
743 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
744                           char * const argv[])
745 {
746         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
747
748         if (argc > 2)
749                 return CMD_RET_USAGE;
750         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
751                 cpld_data->system_rst = CONFIG_RESET;
752         else if (strcmp(argv[1], "init") == 0)
753                 cpld_data->global_rst = INIT_RESET;
754         else
755                 return CMD_RET_USAGE;
756
757         return 0;
758 }
759
760 U_BOOT_CMD(
761         cpld_reset, 2, 0, cpld_reset_cmd,
762         "Reset via CPLD",
763         "conf\n"
764         "       -reset with current CPLD configuration\n"
765         "init\n"
766         "       -reset and initial CPLD configuration with default value"
767
768 );
769
770 static void convert_serdes_mux(int type, int need_reset)
771 {
772         char current_serdes;
773         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
774
775         current_serdes = cpld_data->serdes_mux;
776
777         switch (type) {
778         case LANEB_SATA:
779                 current_serdes &= ~MASK_LANE_B;
780                 break;
781         case LANEB_SGMII1:
782                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
783                 break;
784         case LANEC_SGMII1:
785                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
786                 break;
787         case LANED_SGMII2:
788                 current_serdes |= MASK_LANE_D;
789                 break;
790         case LANEC_PCIEX1:
791                 current_serdes |= MASK_LANE_C;
792                 break;
793         case (LANED_PCIEX2 | LANEC_PCIEX1):
794                 current_serdes |= MASK_LANE_C;
795                 current_serdes &= ~MASK_LANE_D;
796                 break;
797         default:
798                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
799                 return;
800         }
801
802         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
803         cpld_data->serdes_mux = current_serdes;
804
805         if (need_reset == 1) {
806                 printf("Reset board to enable configuration\n");
807                 cpld_data->system_rst = CONFIG_RESET;
808         }
809 }
810
811 void print_serdes_mux(void)
812 {
813         char current_serdes;
814         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
815
816         current_serdes = cpld_data->serdes_mux;
817
818         printf("Serdes Lane B: ");
819         if ((current_serdes & MASK_LANE_B) == 0)
820                 printf("SATA,\n");
821         else
822                 printf("SGMII 1,\n");
823
824         printf("Serdes Lane C: ");
825         if ((current_serdes & MASK_LANE_C) == 0)
826                 printf("SGMII 1,\n");
827         else
828                 printf("PCIe,\n");
829
830         printf("Serdes Lane D: ");
831         if ((current_serdes & MASK_LANE_D) == 0)
832                 printf("PCIe,\n");
833         else
834                 printf("SGMII 2,\n");
835
836         printf("SGMII 1 is on lane ");
837         if ((current_serdes & MASK_SGMII) == 0)
838                 printf("C.\n");
839         else
840                 printf("B.\n");
841 }
842
843 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
844                           char * const argv[])
845 {
846         if (argc != 2)
847                 return CMD_RET_USAGE;
848         if (strcmp(argv[1], "sata") == 0) {
849                 printf("Set serdes lane B to SATA.\n");
850                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
851         } else if (strcmp(argv[1], "sgmii1b") == 0) {
852                 printf("Set serdes lane B to SGMII 1.\n");
853                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
854         } else if (strcmp(argv[1], "sgmii1c") == 0) {
855                 printf("Set serdes lane C to SGMII 1.\n");
856                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
857         } else if (strcmp(argv[1], "sgmii2") == 0) {
858                 printf("Set serdes lane D to SGMII 2.\n");
859                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
860         } else if (strcmp(argv[1], "pciex1") == 0) {
861                 printf("Set serdes lane C to PCIe X1.\n");
862                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
863         } else if (strcmp(argv[1], "pciex2") == 0) {
864                 printf("Set serdes lane C & lane D to PCIe X2.\n");
865                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
866         } else if (strcmp(argv[1], "show") == 0) {
867                 print_serdes_mux();
868         } else {
869                 return CMD_RET_USAGE;
870         }
871
872         return 0;
873 }
874
875 U_BOOT_CMD(
876         lane_bank, 2, 0, serdes_mux_cmd,
877         "Multiplexed function setting for SerDes Lanes",
878         "sata\n"
879         "       -change lane B to sata\n"
880         "lane_bank sgmii1b\n"
881         "       -change lane B to SGMII1\n"
882         "lane_bank sgmii1c\n"
883         "       -change lane C to SGMII1\n"
884         "lane_bank sgmii2\n"
885         "       -change lane D to SGMII2\n"
886         "lane_bank pciex1\n"
887         "       -change lane C to PCIeX1\n"
888         "lane_bank pciex2\n"
889         "       -change lane C & lane D to PCIeX2\n"
890         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
891 );
892 #endif