board/freescale/ls1021atsn/ls1021atsn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright 2016-2019 NXP Semiconductors
   3  */
   4 #include <common.h>
   5 #include <fdt_support.h>
   6 #include <init.h>
   7 #include <asm/arch-ls102xa/ls102xa_soc.h>
   8 #include <asm/arch/ls102xa_devdis.h>
   9 #include <asm/arch/immap_ls102xa.h>
  10 #include <asm/arch/ls102xa_soc.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include "../common/sleep.h"
  13 #include <fsl_validate.h>
  14 #include <fsl_immap.h>
  15 #include <fsl_csu.h>
  16 #include <netdev.h>
  17 #include <spl.h>
  18 #ifdef CONFIG_U_QE
  19 #include <fsl_qe.h>
  20 #endif
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static void ddrmc_init(void)
  25 {
  26 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  27         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  28         u32 temp_sdram_cfg, tmp;
  29
  30         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  31
  32         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  33         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  34
  35         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  36         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  37         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  38         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  39         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  40         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  41
  42 #ifdef CONFIG_DEEP_SLEEP
  43         if (is_warm_boot()) {
  44                 out_be32(&ddr->sdram_cfg_2,
  45                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  46                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  47                 out_be32(&ddr->init_ext_addr, (1 << 31));
  48
  49                 /* DRAM VRef will not be trained */
  50                 out_be32(&ddr->ddr_cdr2,
  51                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  52         } else
  53 #endif
  54         {
  55                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  56                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  57         }
  58
  59         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  60         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  61
  62         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  63
  64         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  65
  66         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  67         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  68
  69         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  70
  71         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  72         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  73
  74         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  75
  76         /* DDR erratum A-009942 */
  77         tmp = in_be32(&ddr->debug[28]);
  78         out_be32(&ddr->debug[28], tmp | 0x0070006f);
  79
  80         udelay(1);
  81
  82 #ifdef CONFIG_DEEP_SLEEP
  83         if (is_warm_boot()) {
  84                 /* enter self-refresh */
  85                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  86                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  87                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  88
  89                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  90         } else
  91 #endif
  92                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  93
  94         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  95
  96 #ifdef CONFIG_DEEP_SLEEP
  97         if (is_warm_boot()) {
  98                 /* exit self-refresh */
  99                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 100                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 101                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 102         }
 103 #endif
 104 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
 105 }
 106
 107 int dram_init(void)
 108 {
 109         ddrmc_init();
 110
 111         erratum_a008850_post();
 112
 113         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 114
 115 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 116         fsl_dp_resume();
 117 #endif
 118
 119         return 0;
 120 }
 121
 122 int board_eth_init(bd_t *bis)
 123 {
 124         return pci_eth_init(bis);
 125 }
 126
 127 int board_early_init_f(void)
 128 {
 129         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 130
 131 #ifdef CONFIG_TSEC_ENET
 132         /*
 133          * Clear BD & FR bits for big endian BD's and frame data (aka set
 134          * correct eTSEC endianness). This is crucial in ensuring that it does
 135          * not report Data Parity Errors in its RX/TX FIFOs when attempting to
 136          * send traffic.
 137          */
 138         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 139         /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
 140         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 141 #endif
 142
 143         arch_soc_init();
 144
 145 #if defined(CONFIG_DEEP_SLEEP)
 146         if (is_warm_boot()) {
 147                 timer_init();
 148                 dram_init();
 149         }
 150 #endif
 151
 152         return 0;
 153 }
 154
 155 #ifdef CONFIG_SPL_BUILD
 156 void board_init_f(ulong dummy)
 157 {
 158         void (*second_uboot)(void);
 159
 160         /* Clear the BSS */
 161         memset(__bss_start, 0, __bss_end - __bss_start);
 162
 163         get_clocks();
 164
 165 #if defined(CONFIG_DEEP_SLEEP)
 166         if (is_warm_boot())
 167                 fsl_dp_disable_console();
 168 #endif
 169
 170         preloader_console_init();
 171
 172         dram_init();
 173
 174         /* Allow OCRAM access permission as R/W */
 175 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 176         enable_layerscape_ns_access();
 177         enable_layerscape_ns_access();
 178 #endif
 179
 180         /*
 181          * if it is woken up from deep sleep, then jump to second
 182          * stage U-Boot and continue executing without recopying
 183          * it from SD since it has already been reserved in memory
 184          * in last boot.
 185          */
 186         if (is_warm_boot()) {
 187                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 188                 second_uboot();
 189         }
 190
 191         board_init_r(NULL, 0);
 192 }
 193 #endif
 194
 195 int board_init(void)
 196 {
 197 #ifndef CONFIG_SYS_FSL_NO_SERDES
 198         fsl_serdes_init();
 199 #endif
 200         ls102xa_smmu_stream_id_init();
 201
 202 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 203         enable_layerscape_ns_access();
 204 #endif
 205
 206 #ifdef CONFIG_U_QE
 207         u_qe_init();
 208 #endif
 209
 210         return 0;
 211 }
 212
 213 #if defined(CONFIG_SPL_BUILD)
 214 void spl_board_init(void)
 215 {
 216         ls102xa_smmu_stream_id_init();
 217 }
 218 #endif
 219
 220 #ifdef CONFIG_BOARD_LATE_INIT
 221 int board_late_init(void)
 222 {
 223 #ifdef CONFIG_CHAIN_OF_TRUST
 224         fsl_setenv_chain_of_trust();
 225 #endif
 226
 227         return 0;
 228 }
 229 #endif
 230
 231 #if defined(CONFIG_MISC_INIT_R)
 232 int misc_init_r(void)
 233 {
 234 #ifdef CONFIG_FSL_DEVICE_DISABLE
 235         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 236 #endif
 237
 238 #ifdef CONFIG_FSL_CAAM
 239         return sec_init();
 240 #endif
 241 }
 242 #endif
 243
 244 #if defined(CONFIG_DEEP_SLEEP)
 245 void board_sleep_prepare(void)
 246 {
 247 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 248         enable_layerscape_ns_access();
 249 #endif
 250 }
 251 #endif
 252
 253 int ft_board_setup(void *blob, bd_t *bd)
 254 {
 255         ft_cpu_setup(blob, bd);
 256
 257 #ifdef CONFIG_PCI
 258         ft_pci_setup(blob, bd);
 259 #endif
 260
 261         return 0;
 262 }