board/freescale/ls1021aqds/ls1021aqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <hwconfig.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <fsl_ifc.h>
  19 #include <fsl_sec.h>
  20 #include <spl.h>
  21
  22 #include "../common/sleep.h"
  23 #include "../common/qixis.h"
  24 #include "ls1021aqds_qixis.h"
  25 #ifdef CONFIG_U_QE
  26 #include "../../../drivers/qe/qe.h"
  27 #endif
  28
  29 #define PIN_MUX_SEL_CAN         0x03
  30 #define PIN_MUX_SEL_IIC2        0xa0
  31 #define PIN_MUX_SEL_RGMII       0x00
  32 #define PIN_MUX_SEL_SAI         0x0c
  33 #define PIN_MUX_SEL_SDHC        0x00
  34
  35 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0x0f) | value)
  36 #define SET_EC_MUX_SEL(reg, value)      ((reg & 0xf0) | value)
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         MUX_TYPE_CAN,
  41         MUX_TYPE_IIC2,
  42         MUX_TYPE_RGMII,
  43         MUX_TYPE_SAI,
  44         MUX_TYPE_SDHC,
  45         MUX_TYPE_SD_PCI4,
  46         MUX_TYPE_SD_PC_SA_SG_SG,
  47         MUX_TYPE_SD_PC_SA_PC_SG,
  48         MUX_TYPE_SD_PC_SG_SG,
  49 };
  50
  51 enum {
  52         GE0_CLK125,
  53         GE2_CLK125,
  54         GE1_CLK125,
  55 };
  56
  57 #ifdef CONFIG_LS102XA_NS_ACCESS
  58 static struct csu_ns_dev ns_dev[] = {
  59         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
  60         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
  61         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
  62         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
  63         { CSU_CSLX_OCRAM, CSU_ALL_RW },
  64         { CSU_CSLX_GIC, CSU_ALL_RW },
  65         { CSU_CSLX_PCIE1, CSU_ALL_RW },
  66         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
  67         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
  68         { CSU_CSLX_PCIE2, CSU_ALL_RW },
  69         { CSU_CSLX_SATA, CSU_ALL_RW },
  70         { CSU_CSLX_USB3, CSU_ALL_RW },
  71         { CSU_CSLX_SERDES, CSU_ALL_RW },
  72         { CSU_CSLX_QDMA, CSU_ALL_RW },
  73         { CSU_CSLX_LPUART2, CSU_ALL_RW },
  74         { CSU_CSLX_LPUART1, CSU_ALL_RW },
  75         { CSU_CSLX_LPUART4, CSU_ALL_RW },
  76         { CSU_CSLX_LPUART3, CSU_ALL_RW },
  77         { CSU_CSLX_LPUART6, CSU_ALL_RW },
  78         { CSU_CSLX_LPUART5, CSU_ALL_RW },
  79         { CSU_CSLX_DSPI2, CSU_ALL_RW },
  80         { CSU_CSLX_DSPI1, CSU_ALL_RW },
  81         { CSU_CSLX_QSPI, CSU_ALL_RW },
  82         { CSU_CSLX_ESDHC, CSU_ALL_RW },
  83         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
  84         { CSU_CSLX_IFC, CSU_ALL_RW },
  85         { CSU_CSLX_I2C1, CSU_ALL_RW },
  86         { CSU_CSLX_USB2, CSU_ALL_RW },
  87         { CSU_CSLX_I2C3, CSU_ALL_RW },
  88         { CSU_CSLX_I2C2, CSU_ALL_RW },
  89         { CSU_CSLX_DUART2, CSU_ALL_RW },
  90         { CSU_CSLX_DUART1, CSU_ALL_RW },
  91         { CSU_CSLX_WDT2, CSU_ALL_RW },
  92         { CSU_CSLX_WDT1, CSU_ALL_RW },
  93         { CSU_CSLX_EDMA, CSU_ALL_RW },
  94         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
  95         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
  96         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
  97         { CSU_CSLX_DDR, CSU_ALL_RW },
  98         { CSU_CSLX_QUICC, CSU_ALL_RW },
  99         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 100         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 101         { CSU_CSLX_SFP, CSU_ALL_RW },
 102         { CSU_CSLX_TMU, CSU_ALL_RW },
 103         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 104         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 105         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 106         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 107         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 108         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 109         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 110         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 111         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 112         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 113         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 114         { CSU_CSLX_CSU, CSU_ALL_RW },
 115         { CSU_CSLX_ASRC, CSU_ALL_RW },
 116         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 117         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 118         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 119         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 120         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 121         { CSU_CSLX_SAI2, CSU_ALL_RW },
 122         { CSU_CSLX_SAI1, CSU_ALL_RW },
 123         { CSU_CSLX_SAI4, CSU_ALL_RW },
 124         { CSU_CSLX_SAI3, CSU_ALL_RW },
 125         { CSU_CSLX_FTM2, CSU_ALL_RW },
 126         { CSU_CSLX_FTM1, CSU_ALL_RW },
 127         { CSU_CSLX_FTM4, CSU_ALL_RW },
 128         { CSU_CSLX_FTM3, CSU_ALL_RW },
 129         { CSU_CSLX_FTM6, CSU_ALL_RW },
 130         { CSU_CSLX_FTM5, CSU_ALL_RW },
 131         { CSU_CSLX_FTM8, CSU_ALL_RW },
 132         { CSU_CSLX_FTM7, CSU_ALL_RW },
 133         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 134         { CSU_CSLX_EPU, CSU_ALL_RW },
 135         { CSU_CSLX_GDI, CSU_ALL_RW },
 136         { CSU_CSLX_DDI, CSU_ALL_RW },
 137         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 138         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 139         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 140 };
 141 #endif
 142
 143 int checkboard(void)
 144 {
 145 #ifndef CONFIG_QSPI_BOOT
 146         char buf[64];
 147 #endif
 148 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
 149         u8 sw;
 150 #endif
 151
 152         puts("Board: LS1021AQDS\n");
 153
 154 #ifdef CONFIG_SD_BOOT
 155         puts("SD\n");
 156 #elif CONFIG_QSPI_BOOT
 157         puts("QSPI\n");
 158 #else
 159         sw = QIXIS_READ(brdcfg[0]);
 160         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 161
 162         if (sw < 0x8)
 163                 printf("vBank: %d\n", sw);
 164         else if (sw == 0x8)
 165                 puts("PromJet\n");
 166         else if (sw == 0x9)
 167                 puts("NAND\n");
 168         else if (sw == 0x15)
 169                 printf("IFCCard\n");
 170         else
 171                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 172 #endif
 173
 174 #ifndef CONFIG_QSPI_BOOT
 175         printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
 176                QIXIS_READ(id), QIXIS_READ(arch));
 177
 178         printf("FPGA:  v%d (%s), build %d\n",
 179                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 180                (int)qixis_read_minor());
 181 #endif
 182
 183         return 0;
 184 }
 185
 186 unsigned long get_board_sys_clk(void)
 187 {
 188         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 189
 190         switch (sysclk_conf & 0x0f) {
 191         case QIXIS_SYSCLK_64:
 192                 return 64000000;
 193         case QIXIS_SYSCLK_83:
 194                 return 83333333;
 195         case QIXIS_SYSCLK_100:
 196                 return 100000000;
 197         case QIXIS_SYSCLK_125:
 198                 return 125000000;
 199         case QIXIS_SYSCLK_133:
 200                 return 133333333;
 201         case QIXIS_SYSCLK_150:
 202                 return 150000000;
 203         case QIXIS_SYSCLK_160:
 204                 return 160000000;
 205         case QIXIS_SYSCLK_166:
 206                 return 166666666;
 207         }
 208         return 66666666;
 209 }
 210
 211 unsigned long get_board_ddr_clk(void)
 212 {
 213         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 214
 215         switch ((ddrclk_conf & 0x30) >> 4) {
 216         case QIXIS_DDRCLK_100:
 217                 return 100000000;
 218         case QIXIS_DDRCLK_125:
 219                 return 125000000;
 220         case QIXIS_DDRCLK_133:
 221                 return 133333333;
 222         }
 223         return 66666666;
 224 }
 225
 226 unsigned int get_soc_major_rev(void)
 227 {
 228         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 229         unsigned int svr, major;
 230
 231         svr = in_be32(&gur->svr);
 232         major = SVR_MAJ(svr);
 233
 234         return major;
 235 }
 236
 237 int select_i2c_ch_pca9547(u8 ch)
 238 {
 239         int ret;
 240
 241         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 242         if (ret) {
 243                 puts("PCA: failed to select proper channel\n");
 244                 return ret;
 245         }
 246
 247         return 0;
 248 }
 249
 250 int dram_init(void)
 251 {
 252         /*
 253          * When resuming from deep sleep, the I2C channel may not be
 254          * in the default channel. So, switch to the default channel
 255          * before accessing DDR SPD.
 256          */
 257         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 258         gd->ram_size = initdram(0);
 259
 260         return 0;
 261 }
 262
 263 #ifdef CONFIG_FSL_ESDHC
 264 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 265         {CONFIG_SYS_FSL_ESDHC_ADDR},
 266 };
 267
 268 int board_mmc_init(bd_t *bis)
 269 {
 270         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 271
 272         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 273 }
 274 #endif
 275
 276 int board_early_init_f(void)
 277 {
 278         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 279         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 280         unsigned int major;
 281
 282 #ifdef CONFIG_TSEC_ENET
 283         /* clear BD & FR bits for BE BD's and frame data */
 284         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 285 #endif
 286
 287 #ifdef CONFIG_FSL_IFC
 288         init_early_memctl_regs();
 289 #endif
 290
 291 #ifdef CONFIG_FSL_QSPI
 292         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 293 #endif
 294
 295 #ifdef CONFIG_FSL_DCU_FB
 296         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 297 #endif
 298
 299         /* Configure Little endian for SAI, ASRC and SPDIF */
 300         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 301
 302         /*
 303          * Enable snoop requests and DVM message requests for
 304          * Slave insterface S4 (A7 core cluster)
 305          */
 306         out_le32(&cci->slave[4].snoop_ctrl,
 307                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 308
 309         major = get_soc_major_rev();
 310         if (major == SOC_MAJOR_VER_1_0) {
 311                 /*
 312                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 313                  * Register All transactions are treated as non-shareable
 314                  */
 315                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 316                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 317
 318                 /* Workaround for the issue that DDR could not respond to
 319                  * barrier transaction which is generated by executing DSB/ISB
 320                  * instruction. Set CCI-400 control override register to
 321                  * terminate the barrier transaction. After DDR is initialized,
 322                  * allow barrier transaction to DDR again */
 323                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 324         }
 325
 326 #if defined(CONFIG_DEEP_SLEEP)
 327         if (is_warm_boot())
 328                 fsl_dp_disable_console();
 329 #endif
 330
 331         return 0;
 332 }
 333
 334 #ifdef CONFIG_SPL_BUILD
 335 void board_init_f(ulong dummy)
 336 {
 337         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 338         unsigned int major;
 339
 340 #ifdef CONFIG_NAND_BOOT
 341         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 342         u32 porsr1, pinctl;
 343
 344         /*
 345          * There is LS1 SoC issue where NOR, FPGA are inaccessible during
 346          * NAND boot because IFC signals > IFC_AD7 are not enabled.
 347          * This workaround changes RCW source to make all signals enabled.
 348          */
 349         porsr1 = in_be32(&gur->porsr1);
 350         pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 351                  DCFG_CCSR_PORSR1_RCW_SRC_I2C);
 352         out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 353                  pinctl);
 354 #endif
 355
 356         /* Clear the BSS */
 357         memset(__bss_start, 0, __bss_end - __bss_start);
 358
 359 #ifdef CONFIG_FSL_IFC
 360         init_early_memctl_regs();
 361 #endif
 362
 363         get_clocks();
 364
 365 #if defined(CONFIG_DEEP_SLEEP)
 366         if (is_warm_boot())
 367                 fsl_dp_disable_console();
 368 #endif
 369
 370         preloader_console_init();
 371
 372 #ifdef CONFIG_SPL_I2C_SUPPORT
 373         i2c_init_all();
 374 #endif
 375
 376         major = get_soc_major_rev();
 377         if (major == SOC_MAJOR_VER_1_0)
 378                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 379
 380         dram_init();
 381
 382         /* Allow OCRAM access permission as R/W */
 383 #ifdef CONFIG_LS102XA_NS_ACCESS
 384         enable_devices_ns_access(&ns_dev[4], 1);
 385         enable_devices_ns_access(&ns_dev[7], 1);
 386 #endif
 387
 388         board_init_r(NULL, 0);
 389 }
 390 #endif
 391
 392 void config_etseccm_source(int etsec_gtx_125_mux)
 393 {
 394         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 395
 396         switch (etsec_gtx_125_mux) {
 397         case GE0_CLK125:
 398                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
 399                 debug("etseccm set to GE0_CLK125\n");
 400                 break;
 401
 402         case GE2_CLK125:
 403                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 404                 debug("etseccm set to GE2_CLK125\n");
 405                 break;
 406
 407         case GE1_CLK125:
 408                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
 409                 debug("etseccm set to GE1_CLK125\n");
 410                 break;
 411
 412         default:
 413                 printf("Error! trying to set etseccm to invalid value\n");
 414                 break;
 415         }
 416 }
 417
 418 int config_board_mux(int ctrl_type)
 419 {
 420         u8 reg12, reg14;
 421
 422         reg12 = QIXIS_READ(brdcfg[12]);
 423         reg14 = QIXIS_READ(brdcfg[14]);
 424
 425         switch (ctrl_type) {
 426         case MUX_TYPE_CAN:
 427                 config_etseccm_source(GE2_CLK125);
 428                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
 429                 break;
 430         case MUX_TYPE_IIC2:
 431                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
 432                 break;
 433         case MUX_TYPE_RGMII:
 434                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
 435                 break;
 436         case MUX_TYPE_SAI:
 437                 config_etseccm_source(GE2_CLK125);
 438                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
 439                 break;
 440         case MUX_TYPE_SDHC:
 441                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
 442                 break;
 443         case MUX_TYPE_SD_PCI4:
 444                 reg12 = 0x38;
 445                 break;
 446         case MUX_TYPE_SD_PC_SA_SG_SG:
 447                 reg12 = 0x01;
 448                 break;
 449         case MUX_TYPE_SD_PC_SA_PC_SG:
 450                 reg12 = 0x01;
 451                 break;
 452         case MUX_TYPE_SD_PC_SG_SG:
 453                 reg12 = 0x21;
 454                 break;
 455         default:
 456                 printf("Wrong mux interface type\n");
 457                 return -1;
 458         }
 459
 460         QIXIS_WRITE(brdcfg[12], reg12);
 461         QIXIS_WRITE(brdcfg[14], reg14);
 462
 463         return 0;
 464 }
 465
 466 int config_serdes_mux(void)
 467 {
 468         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
 469         u32 cfg;
 470
 471         cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 472         cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 473
 474         switch (cfg) {
 475         case 0x0:
 476                 config_board_mux(MUX_TYPE_SD_PCI4);
 477                 break;
 478         case 0x30:
 479                 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
 480                 break;
 481         case 0x60:
 482                 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
 483                 break;
 484         case 0x70:
 485                 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
 486                 break;
 487         default:
 488                 printf("SRDS1 prtcl:0x%x\n", cfg);
 489                 break;
 490         }
 491
 492         return 0;
 493 }
 494
 495 int misc_init_r(void)
 496 {
 497         int conflict_flag;
 498
 499         /* some signals can not enable simultaneous*/
 500         conflict_flag = 0;
 501         if (hwconfig("sdhc"))
 502                 conflict_flag++;
 503         if (hwconfig("iic2"))
 504                 conflict_flag++;
 505         if (conflict_flag > 1) {
 506                 printf("WARNING: pin conflict !\n");
 507                 return 0;
 508         }
 509
 510         conflict_flag = 0;
 511         if (hwconfig("rgmii"))
 512                 conflict_flag++;
 513         if (hwconfig("can"))
 514                 conflict_flag++;
 515         if (hwconfig("sai"))
 516                 conflict_flag++;
 517         if (conflict_flag > 1) {
 518                 printf("WARNING: pin conflict !\n");
 519                 return 0;
 520         }
 521
 522         if (hwconfig("can"))
 523                 config_board_mux(MUX_TYPE_CAN);
 524         else if (hwconfig("rgmii"))
 525                 config_board_mux(MUX_TYPE_RGMII);
 526         else if (hwconfig("sai"))
 527                 config_board_mux(MUX_TYPE_SAI);
 528
 529         if (hwconfig("iic2"))
 530                 config_board_mux(MUX_TYPE_IIC2);
 531         else if (hwconfig("sdhc"))
 532                 config_board_mux(MUX_TYPE_SDHC);
 533
 534 #ifdef CONFIG_FSL_CAAM
 535         return sec_init();
 536 #endif
 537         return 0;
 538 }
 539
 540 struct liodn_id_table sec_liodn_tbl[] = {
 541         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 542         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 543         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 544         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 545         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 546         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 547         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 548         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 549         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 550         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 551         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 552         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 553         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 554         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 555         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 556         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 557 };
 558
 559 struct smmu_stream_id dev_stream_id[] = {
 560         { 0x100, 0x01, "ETSEC MAC1" },
 561         { 0x104, 0x02, "ETSEC MAC2" },
 562         { 0x108, 0x03, "ETSEC MAC3" },
 563         { 0x10c, 0x04, "PEX1" },
 564         { 0x110, 0x05, "PEX2" },
 565         { 0x114, 0x06, "qDMA" },
 566         { 0x118, 0x07, "SATA" },
 567         { 0x11c, 0x08, "USB3" },
 568         { 0x120, 0x09, "QE" },
 569         { 0x124, 0x0a, "eSDHC" },
 570         { 0x128, 0x0b, "eMA" },
 571         { 0x14c, 0x0c, "2D-ACE" },
 572         { 0x150, 0x0d, "USB2" },
 573         { 0x18c, 0x0e, "DEBUG" },
 574 };
 575
 576 int board_init(void)
 577 {
 578         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 579         unsigned int major;
 580
 581         major = get_soc_major_rev();
 582         if (major == SOC_MAJOR_VER_1_0) {
 583                 /* Set CCI-400 control override register to
 584                  * enable barrier transaction */
 585                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 586         }
 587
 588         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 589
 590 #ifndef CONFIG_SYS_FSL_NO_SERDES
 591         fsl_serdes_init();
 592         config_serdes_mux();
 593 #endif
 594
 595         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 596                                       ARRAY_SIZE(sec_liodn_tbl));
 597         ls102xa_config_smmu_stream_id(dev_stream_id,
 598                                       ARRAY_SIZE(dev_stream_id));
 599
 600 #ifdef CONFIG_LS102XA_NS_ACCESS
 601         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 602 #endif
 603
 604 #ifdef CONFIG_U_QE
 605         u_qe_init();
 606 #endif
 607
 608         return 0;
 609 }
 610
 611 #if defined(CONFIG_DEEP_SLEEP)
 612 void board_sleep_prepare(void)
 613 {
 614         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 615         unsigned int major;
 616
 617         major = get_soc_major_rev();
 618         if (major == SOC_MAJOR_VER_1_0) {
 619                 /* Set CCI-400 control override register to
 620                  * enable barrier transaction */
 621                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 622         }
 623
 624
 625 #ifdef CONFIG_LS102XA_NS_ACCESS
 626         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 627 #endif
 628 }
 629 #endif
 630
 631 int ft_board_setup(void *blob, bd_t *bd)
 632 {
 633         ft_cpu_setup(blob, bd);
 634
 635 #ifdef CONFIG_PCI
 636         ft_pci_setup(blob, bd);
 637 #endif
 638
 639         return 0;
 640 }
 641
 642 u8 flash_read8(void *addr)
 643 {
 644         return __raw_readb(addr + 1);
 645 }
 646
 647 void flash_write16(u16 val, void *addr)
 648 {
 649         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 650
 651         __raw_writew(shftval, addr);
 652 }
 653
 654 u16 flash_read16(void *addr)
 655 {
 656         u16 val = __raw_readw(addr);
 657
 658         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 659 }