board/freescale/ls1021aqds/ls1021aqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <asm/pcie_layerscape.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <fsl_ifc.h>
  20 #include <fsl_sec.h>
  21 #include <spl.h>
  22
  23 #include "../common/sleep.h"
  24 #include "../common/qixis.h"
  25 #include "ls1021aqds_qixis.h"
  26 #ifdef CONFIG_U_QE
  27 #include "../../../drivers/qe/qe.h"
  28 #endif
  29
  30 #define PIN_MUX_SEL_CAN         0x03
  31 #define PIN_MUX_SEL_IIC2        0xa0
  32 #define PIN_MUX_SEL_RGMII       0x00
  33 #define PIN_MUX_SEL_SAI         0x0c
  34 #define PIN_MUX_SEL_SDHC        0x00
  35
  36 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0x0f) | value)
  37 #define SET_EC_MUX_SEL(reg, value)      ((reg & 0xf0) | value)
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 enum {
  41         MUX_TYPE_CAN,
  42         MUX_TYPE_IIC2,
  43         MUX_TYPE_RGMII,
  44         MUX_TYPE_SAI,
  45         MUX_TYPE_SDHC,
  46         MUX_TYPE_SD_PCI4,
  47         MUX_TYPE_SD_PC_SA_SG_SG,
  48         MUX_TYPE_SD_PC_SA_PC_SG,
  49         MUX_TYPE_SD_PC_SG_SG,
  50 };
  51
  52 enum {
  53         GE0_CLK125,
  54         GE2_CLK125,
  55         GE1_CLK125,
  56 };
  57
  58 int checkboard(void)
  59 {
  60 #ifndef CONFIG_QSPI_BOOT
  61         char buf[64];
  62 #endif
  63 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  64         u8 sw;
  65 #endif
  66
  67         puts("Board: LS1021AQDS\n");
  68
  69 #ifdef CONFIG_SD_BOOT
  70         puts("SD\n");
  71 #elif CONFIG_QSPI_BOOT
  72         puts("QSPI\n");
  73 #else
  74         sw = QIXIS_READ(brdcfg[0]);
  75         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  76
  77         if (sw < 0x8)
  78                 printf("vBank: %d\n", sw);
  79         else if (sw == 0x8)
  80                 puts("PromJet\n");
  81         else if (sw == 0x9)
  82                 puts("NAND\n");
  83         else if (sw == 0x15)
  84                 printf("IFCCard\n");
  85         else
  86                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  87 #endif
  88
  89 #ifndef CONFIG_QSPI_BOOT
  90         printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  91                QIXIS_READ(id), QIXIS_READ(arch));
  92
  93         printf("FPGA:  v%d (%s), build %d\n",
  94                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  95                (int)qixis_read_minor());
  96 #endif
  97
  98         return 0;
  99 }
 100
 101 unsigned long get_board_sys_clk(void)
 102 {
 103         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 104
 105         switch (sysclk_conf & 0x0f) {
 106         case QIXIS_SYSCLK_64:
 107                 return 64000000;
 108         case QIXIS_SYSCLK_83:
 109                 return 83333333;
 110         case QIXIS_SYSCLK_100:
 111                 return 100000000;
 112         case QIXIS_SYSCLK_125:
 113                 return 125000000;
 114         case QIXIS_SYSCLK_133:
 115                 return 133333333;
 116         case QIXIS_SYSCLK_150:
 117                 return 150000000;
 118         case QIXIS_SYSCLK_160:
 119                 return 160000000;
 120         case QIXIS_SYSCLK_166:
 121                 return 166666666;
 122         }
 123         return 66666666;
 124 }
 125
 126 unsigned long get_board_ddr_clk(void)
 127 {
 128         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 129
 130         switch ((ddrclk_conf & 0x30) >> 4) {
 131         case QIXIS_DDRCLK_100:
 132                 return 100000000;
 133         case QIXIS_DDRCLK_125:
 134                 return 125000000;
 135         case QIXIS_DDRCLK_133:
 136                 return 133333333;
 137         }
 138         return 66666666;
 139 }
 140
 141 int select_i2c_ch_pca9547(u8 ch)
 142 {
 143         int ret;
 144
 145         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 146         if (ret) {
 147                 puts("PCA: failed to select proper channel\n");
 148                 return ret;
 149         }
 150
 151         return 0;
 152 }
 153
 154 int dram_init(void)
 155 {
 156         /*
 157          * When resuming from deep sleep, the I2C channel may not be
 158          * in the default channel. So, switch to the default channel
 159          * before accessing DDR SPD.
 160          */
 161         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 162         gd->ram_size = initdram(0);
 163
 164         return 0;
 165 }
 166
 167 #ifdef CONFIG_FSL_ESDHC
 168 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 169         {CONFIG_SYS_FSL_ESDHC_ADDR},
 170 };
 171
 172 int board_mmc_init(bd_t *bis)
 173 {
 174         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 175
 176         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 177 }
 178 #endif
 179
 180 int board_early_init_f(void)
 181 {
 182         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 183         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 184
 185 #ifdef CONFIG_TSEC_ENET
 186         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 187 #endif
 188
 189 #ifdef CONFIG_FSL_IFC
 190         init_early_memctl_regs();
 191 #endif
 192
 193 #ifdef CONFIG_FSL_QSPI
 194         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 195 #endif
 196
 197 #ifdef CONFIG_FSL_DCU_FB
 198         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 199 #endif
 200
 201         /*
 202          * Enable snoop requests and DVM message requests for
 203          * Slave insterface S4 (A7 core cluster)
 204          */
 205         out_le32(&cci->slave[4].snoop_ctrl,
 206                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 207
 208         /*
 209          * Set CCI-400 Slave interface S1, S2 Shareable Override Register
 210          * All transactions are treated as non-shareable
 211          */
 212         out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 213         out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 214
 215         /* Workaround for the issue that DDR could not respond to
 216          * barrier transaction which is generated by executing DSB/ISB
 217          * instruction. Set CCI-400 control override register to
 218          * terminate the barrier transaction. After DDR is initialized,
 219          * allow barrier transaction to DDR again */
 220         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 221
 222 #if defined(CONFIG_DEEP_SLEEP)
 223         if (is_warm_boot())
 224                 fsl_dp_disable_console();
 225 #endif
 226
 227         return 0;
 228 }
 229
 230 #ifdef CONFIG_SPL_BUILD
 231 void board_init_f(ulong dummy)
 232 {
 233         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 234
 235 #ifdef CONFIG_NAND_BOOT
 236         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 237         u32 porsr1, pinctl;
 238
 239         /*
 240          * There is LS1 SoC issue where NOR, FPGA are inaccessible during
 241          * NAND boot because IFC signals > IFC_AD7 are not enabled.
 242          * This workaround changes RCW source to make all signals enabled.
 243          */
 244         porsr1 = in_be32(&gur->porsr1);
 245         pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 246                  DCFG_CCSR_PORSR1_RCW_SRC_I2C);
 247         out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 248                  pinctl);
 249 #endif
 250
 251         /* Clear the BSS */
 252         memset(__bss_start, 0, __bss_end - __bss_start);
 253
 254 #ifdef CONFIG_FSL_IFC
 255         init_early_memctl_regs();
 256 #endif
 257
 258         get_clocks();
 259
 260 #if defined(CONFIG_DEEP_SLEEP)
 261         if (is_warm_boot())
 262                 fsl_dp_disable_console();
 263 #endif
 264
 265         preloader_console_init();
 266
 267 #ifdef CONFIG_SPL_I2C_SUPPORT
 268         i2c_init_all();
 269 #endif
 270         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 271
 272         dram_init();
 273
 274         board_init_r(NULL, 0);
 275 }
 276 #endif
 277
 278 void config_etseccm_source(int etsec_gtx_125_mux)
 279 {
 280         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 281
 282         switch (etsec_gtx_125_mux) {
 283         case GE0_CLK125:
 284                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
 285                 debug("etseccm set to GE0_CLK125\n");
 286                 break;
 287
 288         case GE2_CLK125:
 289                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 290                 debug("etseccm set to GE2_CLK125\n");
 291                 break;
 292
 293         case GE1_CLK125:
 294                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
 295                 debug("etseccm set to GE1_CLK125\n");
 296                 break;
 297
 298         default:
 299                 printf("Error! trying to set etseccm to invalid value\n");
 300                 break;
 301         }
 302 }
 303
 304 int config_board_mux(int ctrl_type)
 305 {
 306         u8 reg12, reg14;
 307
 308         reg12 = QIXIS_READ(brdcfg[12]);
 309         reg14 = QIXIS_READ(brdcfg[14]);
 310
 311         switch (ctrl_type) {
 312         case MUX_TYPE_CAN:
 313                 config_etseccm_source(GE2_CLK125);
 314                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
 315                 break;
 316         case MUX_TYPE_IIC2:
 317                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
 318                 break;
 319         case MUX_TYPE_RGMII:
 320                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
 321                 break;
 322         case MUX_TYPE_SAI:
 323                 config_etseccm_source(GE2_CLK125);
 324                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
 325                 break;
 326         case MUX_TYPE_SDHC:
 327                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
 328                 break;
 329         case MUX_TYPE_SD_PCI4:
 330                 reg12 = 0x38;
 331                 break;
 332         case MUX_TYPE_SD_PC_SA_SG_SG:
 333                 reg12 = 0x01;
 334                 break;
 335         case MUX_TYPE_SD_PC_SA_PC_SG:
 336                 reg12 = 0x01;
 337                 break;
 338         case MUX_TYPE_SD_PC_SG_SG:
 339                 reg12 = 0x21;
 340                 break;
 341         default:
 342                 printf("Wrong mux interface type\n");
 343                 return -1;
 344         }
 345
 346         QIXIS_WRITE(brdcfg[12], reg12);
 347         QIXIS_WRITE(brdcfg[14], reg14);
 348
 349         return 0;
 350 }
 351
 352 int config_serdes_mux(void)
 353 {
 354         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
 355         u32 cfg;
 356
 357         cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 358         cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 359
 360         switch (cfg) {
 361         case 0x0:
 362                 config_board_mux(MUX_TYPE_SD_PCI4);
 363                 break;
 364         case 0x30:
 365                 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
 366                 break;
 367         case 0x60:
 368                 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
 369                 break;
 370         case 0x70:
 371                 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
 372                 break;
 373         default:
 374                 printf("SRDS1 prtcl:0x%x\n", cfg);
 375                 break;
 376         }
 377
 378         return 0;
 379 }
 380
 381 int misc_init_r(void)
 382 {
 383         int conflict_flag;
 384
 385         /* some signals can not enable simultaneous*/
 386         conflict_flag = 0;
 387         if (hwconfig("sdhc"))
 388                 conflict_flag++;
 389         if (hwconfig("iic2"))
 390                 conflict_flag++;
 391         if (conflict_flag > 1) {
 392                 printf("WARNING: pin conflict !\n");
 393                 return 0;
 394         }
 395
 396         conflict_flag = 0;
 397         if (hwconfig("rgmii"))
 398                 conflict_flag++;
 399         if (hwconfig("can"))
 400                 conflict_flag++;
 401         if (hwconfig("sai"))
 402                 conflict_flag++;
 403         if (conflict_flag > 1) {
 404                 printf("WARNING: pin conflict !\n");
 405                 return 0;
 406         }
 407
 408         if (hwconfig("can"))
 409                 config_board_mux(MUX_TYPE_CAN);
 410         else if (hwconfig("rgmii"))
 411                 config_board_mux(MUX_TYPE_RGMII);
 412         else if (hwconfig("sai"))
 413                 config_board_mux(MUX_TYPE_SAI);
 414
 415         if (hwconfig("iic2"))
 416                 config_board_mux(MUX_TYPE_IIC2);
 417         else if (hwconfig("sdhc"))
 418                 config_board_mux(MUX_TYPE_SDHC);
 419
 420 #ifdef CONFIG_FSL_CAAM
 421         return sec_init();
 422 #endif
 423         return 0;
 424 }
 425
 426 #ifdef CONFIG_LS102XA_NS_ACCESS
 427 static struct csu_ns_dev ns_dev[] = {
 428         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 429         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 430         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 431         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 432         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 433         { CSU_CSLX_GIC, CSU_ALL_RW },
 434         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 435         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 436         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 437         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 438         { CSU_CSLX_SATA, CSU_ALL_RW },
 439         { CSU_CSLX_USB3, CSU_ALL_RW },
 440         { CSU_CSLX_SERDES, CSU_ALL_RW },
 441         { CSU_CSLX_QDMA, CSU_ALL_RW },
 442         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 443         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 444         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 445         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 446         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 447         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 448         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 449         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 450         { CSU_CSLX_QSPI, CSU_ALL_RW },
 451         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 452         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 453         { CSU_CSLX_IFC, CSU_ALL_RW },
 454         { CSU_CSLX_I2C1, CSU_ALL_RW },
 455         { CSU_CSLX_USB2, CSU_ALL_RW },
 456         { CSU_CSLX_I2C3, CSU_ALL_RW },
 457         { CSU_CSLX_I2C2, CSU_ALL_RW },
 458         { CSU_CSLX_DUART2, CSU_ALL_RW },
 459         { CSU_CSLX_DUART1, CSU_ALL_RW },
 460         { CSU_CSLX_WDT2, CSU_ALL_RW },
 461         { CSU_CSLX_WDT1, CSU_ALL_RW },
 462         { CSU_CSLX_EDMA, CSU_ALL_RW },
 463         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 464         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 465         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 466         { CSU_CSLX_DDR, CSU_ALL_RW },
 467         { CSU_CSLX_QUICC, CSU_ALL_RW },
 468         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 469         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 470         { CSU_CSLX_SFP, CSU_ALL_RW },
 471         { CSU_CSLX_TMU, CSU_ALL_RW },
 472         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 473         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 474         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 475         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 476         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 477         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 478         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 479         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 480         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 481         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 482         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 483         { CSU_CSLX_CSU, CSU_ALL_RW },
 484         { CSU_CSLX_ASRC, CSU_ALL_RW },
 485         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 486         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 487         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 488         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 489         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 490         { CSU_CSLX_SAI2, CSU_ALL_RW },
 491         { CSU_CSLX_SAI1, CSU_ALL_RW },
 492         { CSU_CSLX_SAI4, CSU_ALL_RW },
 493         { CSU_CSLX_SAI3, CSU_ALL_RW },
 494         { CSU_CSLX_FTM2, CSU_ALL_RW },
 495         { CSU_CSLX_FTM1, CSU_ALL_RW },
 496         { CSU_CSLX_FTM4, CSU_ALL_RW },
 497         { CSU_CSLX_FTM3, CSU_ALL_RW },
 498         { CSU_CSLX_FTM6, CSU_ALL_RW },
 499         { CSU_CSLX_FTM5, CSU_ALL_RW },
 500         { CSU_CSLX_FTM8, CSU_ALL_RW },
 501         { CSU_CSLX_FTM7, CSU_ALL_RW },
 502         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 503         { CSU_CSLX_EPU, CSU_ALL_RW },
 504         { CSU_CSLX_GDI, CSU_ALL_RW },
 505         { CSU_CSLX_DDI, CSU_ALL_RW },
 506         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 507         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 508         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 509 };
 510 #endif
 511
 512 struct smmu_stream_id dev_stream_id[] = {
 513         { 0x100, 0x01, "ETSEC MAC1" },
 514         { 0x104, 0x02, "ETSEC MAC2" },
 515         { 0x108, 0x03, "ETSEC MAC3" },
 516         { 0x10c, 0x04, "PEX1" },
 517         { 0x110, 0x05, "PEX2" },
 518         { 0x114, 0x06, "qDMA" },
 519         { 0x118, 0x07, "SATA" },
 520         { 0x11c, 0x08, "USB3" },
 521         { 0x120, 0x09, "QE" },
 522         { 0x124, 0x0a, "eSDHC" },
 523         { 0x128, 0x0b, "eMA" },
 524         { 0x14c, 0x0c, "2D-ACE" },
 525         { 0x150, 0x0d, "USB2" },
 526         { 0x18c, 0x0e, "DEBUG" },
 527 };
 528
 529 int board_init(void)
 530 {
 531         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 532
 533         /* Set CCI-400 control override register to
 534          * enable barrier transaction */
 535         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 536
 537         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 538
 539 #ifndef CONFIG_SYS_FSL_NO_SERDES
 540         fsl_serdes_init();
 541         config_serdes_mux();
 542 #endif
 543
 544         ls102xa_config_smmu_stream_id(dev_stream_id,
 545                                       ARRAY_SIZE(dev_stream_id));
 546
 547 #ifdef CONFIG_LS102XA_NS_ACCESS
 548         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 549 #endif
 550
 551 #ifdef CONFIG_U_QE
 552         u_qe_init();
 553 #endif
 554
 555         return 0;
 556 }
 557
 558 #if defined(CONFIG_DEEP_SLEEP)
 559 void board_sleep_prepare(void)
 560 {
 561         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 562
 563         /* Set CCI-400 control override register to
 564          * enable barrier transaction */
 565         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 566
 567 #ifdef CONFIG_LS102XA_NS_ACCESS
 568         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 569 #endif
 570 }
 571 #endif
 572
 573 int ft_board_setup(void *blob, bd_t *bd)
 574 {
 575         ft_cpu_setup(blob, bd);
 576
 577 #ifdef CONFIG_PCIE_LAYERSCAPE
 578         ft_pcie_setup(blob, bd);
 579 #endif
 580
 581         return 0;
 582 }
 583
 584 u8 flash_read8(void *addr)
 585 {
 586         return __raw_readb(addr + 1);
 587 }
 588
 589 void flash_write16(u16 val, void *addr)
 590 {
 591         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 592
 593         __raw_writew(shftval, addr);
 594 }
 595
 596 u16 flash_read16(void *addr)
 597 {
 598         u16 val = __raw_readw(addr);
 599
 600         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 601 }