2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/pcie_layerscape.h>
15 #include <fsl_esdhc.h>
19 #include "../common/qixis.h"
20 #include "ls1021aqds_qixis.h"
22 #include "../../../drivers/qe/qe.h"
25 DECLARE_GLOBAL_DATA_PTR;
29 MUX_TYPE_SD_PC_SA_SG_SG,
30 MUX_TYPE_SD_PC_SA_PC_SG,
39 puts("Board: LS1021AQDS\n");
41 sw = QIXIS_READ(brdcfg[0]);
42 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
45 printf("vBank: %d\n", sw);
53 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
55 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
56 QIXIS_READ(id), QIXIS_READ(arch));
58 printf("FPGA: v%d (%s), build %d\n",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor());
65 unsigned long get_board_sys_clk(void)
67 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
69 switch (sysclk_conf & 0x0f) {
74 case QIXIS_SYSCLK_100:
76 case QIXIS_SYSCLK_125:
78 case QIXIS_SYSCLK_133:
80 case QIXIS_SYSCLK_150:
82 case QIXIS_SYSCLK_160:
84 case QIXIS_SYSCLK_166:
90 unsigned long get_board_ddr_clk(void)
92 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
94 switch ((ddrclk_conf & 0x30) >> 4) {
95 case QIXIS_DDRCLK_100:
97 case QIXIS_DDRCLK_125:
99 case QIXIS_DDRCLK_133:
107 gd->ram_size = initdram(0);
112 #ifdef CONFIG_FSL_ESDHC
113 struct fsl_esdhc_cfg esdhc_cfg[1] = {
114 {CONFIG_SYS_FSL_ESDHC_ADDR},
117 int board_mmc_init(bd_t *bis)
119 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
121 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
125 int select_i2c_ch_pca9547(u8 ch)
129 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
131 puts("PCA: failed to select proper channel\n");
138 int board_early_init_f(void)
140 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
141 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
143 #ifdef CONFIG_TSEC_ENET
144 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
145 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
148 #ifdef CONFIG_FSL_IFC
149 init_early_memctl_regs();
152 /* Workaround for the issue that DDR could not respond to
153 * barrier transaction which is generated by executing DSB/ISB
154 * instruction. Set CCI-400 control override register to
155 * terminate the barrier transaction. After DDR is initialized,
156 * allow barrier transaction to DDR again */
157 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
162 int config_board_mux(int ctrl_type)
166 reg12 = QIXIS_READ(brdcfg[12]);
169 case MUX_TYPE_SD_PCI4:
172 case MUX_TYPE_SD_PC_SA_SG_SG:
175 case MUX_TYPE_SD_PC_SA_PC_SG:
178 case MUX_TYPE_SD_PC_SG_SG:
182 printf("Wrong mux interface type\n");
186 QIXIS_WRITE(brdcfg[12], reg12);
191 int config_serdes_mux(void)
193 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
196 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
197 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
201 config_board_mux(MUX_TYPE_SD_PCI4);
204 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
207 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
210 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
213 printf("SRDS1 prtcl:0x%x\n", cfg);
220 #if defined(CONFIG_MISC_INIT_R)
221 int misc_init_r(void)
223 #ifdef CONFIG_FSL_CAAM
231 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
233 /* Set CCI-400 control override register to
234 * enable barrier transaction */
235 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
237 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
238 * All transactions are treated as non-shareable
240 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
241 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
242 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
244 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
246 #ifndef CONFIG_SYS_FSL_NO_SERDES
258 int ft_board_setup(void *blob, bd_t *bd)
260 ft_cpu_setup(blob, bd);
262 #ifdef CONFIG_PCIE_LAYERSCAPE
263 ft_pcie_setup(blob, bd);
269 u8 flash_read8(void *addr)
271 return __raw_readb(addr + 1);
274 void flash_write16(u16 val, void *addr)
276 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
278 __raw_writew(shftval, addr);
281 u16 flash_read16(void *addr)
283 u16 val = __raw_readw(addr);
285 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);