2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ns_access.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ls102xa_stream_id.h>
17 #include <fsl_esdhc.h>
22 #include "../common/sleep.h"
23 #include "../common/qixis.h"
24 #include "ls1021aqds_qixis.h"
26 #include "../../../drivers/qe/qe.h"
29 #define PIN_MUX_SEL_CAN 0x03
30 #define PIN_MUX_SEL_IIC2 0xa0
31 #define PIN_MUX_SEL_RGMII 0x00
32 #define PIN_MUX_SEL_SAI 0x0c
33 #define PIN_MUX_SEL_SDHC 0x00
35 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
36 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
37 DECLARE_GLOBAL_DATA_PTR;
46 MUX_TYPE_SD_PC_SA_SG_SG,
47 MUX_TYPE_SD_PC_SA_PC_SG,
57 #ifdef CONFIG_LS102XA_NS_ACCESS
58 static struct csu_ns_dev ns_dev[] = {
59 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
60 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
61 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
62 { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
63 { CSU_CSLX_OCRAM, CSU_ALL_RW },
64 { CSU_CSLX_GIC, CSU_ALL_RW },
65 { CSU_CSLX_PCIE1, CSU_ALL_RW },
66 { CSU_CSLX_OCRAM2, CSU_ALL_RW },
67 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
68 { CSU_CSLX_PCIE2, CSU_ALL_RW },
69 { CSU_CSLX_SATA, CSU_ALL_RW },
70 { CSU_CSLX_USB3, CSU_ALL_RW },
71 { CSU_CSLX_SERDES, CSU_ALL_RW },
72 { CSU_CSLX_QDMA, CSU_ALL_RW },
73 { CSU_CSLX_LPUART2, CSU_ALL_RW },
74 { CSU_CSLX_LPUART1, CSU_ALL_RW },
75 { CSU_CSLX_LPUART4, CSU_ALL_RW },
76 { CSU_CSLX_LPUART3, CSU_ALL_RW },
77 { CSU_CSLX_LPUART6, CSU_ALL_RW },
78 { CSU_CSLX_LPUART5, CSU_ALL_RW },
79 { CSU_CSLX_DSPI2, CSU_ALL_RW },
80 { CSU_CSLX_DSPI1, CSU_ALL_RW },
81 { CSU_CSLX_QSPI, CSU_ALL_RW },
82 { CSU_CSLX_ESDHC, CSU_ALL_RW },
83 { CSU_CSLX_2D_ACE, CSU_ALL_RW },
84 { CSU_CSLX_IFC, CSU_ALL_RW },
85 { CSU_CSLX_I2C1, CSU_ALL_RW },
86 { CSU_CSLX_USB2, CSU_ALL_RW },
87 { CSU_CSLX_I2C3, CSU_ALL_RW },
88 { CSU_CSLX_I2C2, CSU_ALL_RW },
89 { CSU_CSLX_DUART2, CSU_ALL_RW },
90 { CSU_CSLX_DUART1, CSU_ALL_RW },
91 { CSU_CSLX_WDT2, CSU_ALL_RW },
92 { CSU_CSLX_WDT1, CSU_ALL_RW },
93 { CSU_CSLX_EDMA, CSU_ALL_RW },
94 { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
95 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
96 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
97 { CSU_CSLX_DDR, CSU_ALL_RW },
98 { CSU_CSLX_QUICC, CSU_ALL_RW },
99 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
100 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
101 { CSU_CSLX_SFP, CSU_ALL_RW },
102 { CSU_CSLX_TMU, CSU_ALL_RW },
103 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
104 { CSU_CSLX_RESERVED0, CSU_ALL_RW },
105 { CSU_CSLX_ETSEC1, CSU_ALL_RW },
106 { CSU_CSLX_SEC5_5, CSU_ALL_RW },
107 { CSU_CSLX_ETSEC3, CSU_ALL_RW },
108 { CSU_CSLX_ETSEC2, CSU_ALL_RW },
109 { CSU_CSLX_GPIO2, CSU_ALL_RW },
110 { CSU_CSLX_GPIO1, CSU_ALL_RW },
111 { CSU_CSLX_GPIO4, CSU_ALL_RW },
112 { CSU_CSLX_GPIO3, CSU_ALL_RW },
113 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
114 { CSU_CSLX_CSU, CSU_ALL_RW },
115 { CSU_CSLX_ASRC, CSU_ALL_RW },
116 { CSU_CSLX_SPDIF, CSU_ALL_RW },
117 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
118 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
119 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
120 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
121 { CSU_CSLX_SAI2, CSU_ALL_RW },
122 { CSU_CSLX_SAI1, CSU_ALL_RW },
123 { CSU_CSLX_SAI4, CSU_ALL_RW },
124 { CSU_CSLX_SAI3, CSU_ALL_RW },
125 { CSU_CSLX_FTM2, CSU_ALL_RW },
126 { CSU_CSLX_FTM1, CSU_ALL_RW },
127 { CSU_CSLX_FTM4, CSU_ALL_RW },
128 { CSU_CSLX_FTM3, CSU_ALL_RW },
129 { CSU_CSLX_FTM6, CSU_ALL_RW },
130 { CSU_CSLX_FTM5, CSU_ALL_RW },
131 { CSU_CSLX_FTM8, CSU_ALL_RW },
132 { CSU_CSLX_FTM7, CSU_ALL_RW },
133 { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
134 { CSU_CSLX_EPU, CSU_ALL_RW },
135 { CSU_CSLX_GDI, CSU_ALL_RW },
136 { CSU_CSLX_DDI, CSU_ALL_RW },
137 { CSU_CSLX_RESERVED1, CSU_ALL_RW },
138 { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
139 { CSU_CSLX_RESERVED2, CSU_ALL_RW },
145 #ifndef CONFIG_QSPI_BOOT
148 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
152 puts("Board: LS1021AQDS\n");
154 #ifdef CONFIG_SD_BOOT
156 #elif CONFIG_QSPI_BOOT
159 sw = QIXIS_READ(brdcfg[0]);
160 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
163 printf("vBank: %d\n", sw);
171 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
174 #ifndef CONFIG_QSPI_BOOT
175 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
176 QIXIS_READ(id), QIXIS_READ(arch));
178 printf("FPGA: v%d (%s), build %d\n",
179 (int)QIXIS_READ(scver), qixis_read_tag(buf),
180 (int)qixis_read_minor());
186 unsigned long get_board_sys_clk(void)
188 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
190 switch (sysclk_conf & 0x0f) {
191 case QIXIS_SYSCLK_64:
193 case QIXIS_SYSCLK_83:
195 case QIXIS_SYSCLK_100:
197 case QIXIS_SYSCLK_125:
199 case QIXIS_SYSCLK_133:
201 case QIXIS_SYSCLK_150:
203 case QIXIS_SYSCLK_160:
205 case QIXIS_SYSCLK_166:
211 unsigned long get_board_ddr_clk(void)
213 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
215 switch ((ddrclk_conf & 0x30) >> 4) {
216 case QIXIS_DDRCLK_100:
218 case QIXIS_DDRCLK_125:
220 case QIXIS_DDRCLK_133:
226 unsigned int get_soc_major_rev(void)
228 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
229 unsigned int svr, major;
231 svr = in_be32(&gur->svr);
232 major = SVR_MAJ(svr);
237 int select_i2c_ch_pca9547(u8 ch)
241 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
243 puts("PCA: failed to select proper channel\n");
253 * When resuming from deep sleep, the I2C channel may not be
254 * in the default channel. So, switch to the default channel
255 * before accessing DDR SPD.
257 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
258 gd->ram_size = initdram(0);
263 #ifdef CONFIG_FSL_ESDHC
264 struct fsl_esdhc_cfg esdhc_cfg[1] = {
265 {CONFIG_SYS_FSL_ESDHC_ADDR},
268 int board_mmc_init(bd_t *bis)
270 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
272 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
276 int board_early_init_f(void)
278 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
279 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
282 #ifdef CONFIG_TSEC_ENET
283 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
286 #ifdef CONFIG_FSL_IFC
287 init_early_memctl_regs();
290 #ifdef CONFIG_FSL_QSPI
291 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
294 #ifdef CONFIG_FSL_DCU_FB
295 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
298 /* Configure Little endian for SAI, ASRC and SPDIF */
299 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
302 * Enable snoop requests and DVM message requests for
303 * Slave insterface S4 (A7 core cluster)
305 out_le32(&cci->slave[4].snoop_ctrl,
306 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
308 major = get_soc_major_rev();
309 if (major == SOC_MAJOR_VER_1_0) {
311 * Set CCI-400 Slave interface S1, S2 Shareable Override
312 * Register All transactions are treated as non-shareable
314 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
315 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
317 /* Workaround for the issue that DDR could not respond to
318 * barrier transaction which is generated by executing DSB/ISB
319 * instruction. Set CCI-400 control override register to
320 * terminate the barrier transaction. After DDR is initialized,
321 * allow barrier transaction to DDR again */
322 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
325 #if defined(CONFIG_DEEP_SLEEP)
327 fsl_dp_disable_console();
333 #ifdef CONFIG_SPL_BUILD
334 void board_init_f(ulong dummy)
336 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
339 #ifdef CONFIG_NAND_BOOT
340 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
344 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
345 * NAND boot because IFC signals > IFC_AD7 are not enabled.
346 * This workaround changes RCW source to make all signals enabled.
348 porsr1 = in_be32(&gur->porsr1);
349 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
350 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
351 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
356 memset(__bss_start, 0, __bss_end - __bss_start);
358 #ifdef CONFIG_FSL_IFC
359 init_early_memctl_regs();
364 #if defined(CONFIG_DEEP_SLEEP)
366 fsl_dp_disable_console();
369 preloader_console_init();
371 #ifdef CONFIG_SPL_I2C_SUPPORT
375 major = get_soc_major_rev();
376 if (major == SOC_MAJOR_VER_1_0)
377 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
381 /* Allow OCRAM access permission as R/W */
382 #ifdef CONFIG_LS102XA_NS_ACCESS
383 enable_devices_ns_access(&ns_dev[4], 1);
384 enable_devices_ns_access(&ns_dev[7], 1);
387 board_init_r(NULL, 0);
391 void config_etseccm_source(int etsec_gtx_125_mux)
393 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
395 switch (etsec_gtx_125_mux) {
397 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
398 debug("etseccm set to GE0_CLK125\n");
402 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
403 debug("etseccm set to GE2_CLK125\n");
407 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
408 debug("etseccm set to GE1_CLK125\n");
412 printf("Error! trying to set etseccm to invalid value\n");
417 int config_board_mux(int ctrl_type)
421 reg12 = QIXIS_READ(brdcfg[12]);
422 reg14 = QIXIS_READ(brdcfg[14]);
426 config_etseccm_source(GE2_CLK125);
427 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
430 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
433 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
436 config_etseccm_source(GE2_CLK125);
437 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
440 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
442 case MUX_TYPE_SD_PCI4:
445 case MUX_TYPE_SD_PC_SA_SG_SG:
448 case MUX_TYPE_SD_PC_SA_PC_SG:
451 case MUX_TYPE_SD_PC_SG_SG:
455 printf("Wrong mux interface type\n");
459 QIXIS_WRITE(brdcfg[12], reg12);
460 QIXIS_WRITE(brdcfg[14], reg14);
465 int config_serdes_mux(void)
467 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
470 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
471 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
475 config_board_mux(MUX_TYPE_SD_PCI4);
478 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
481 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
484 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
487 printf("SRDS1 prtcl:0x%x\n", cfg);
494 int misc_init_r(void)
498 /* some signals can not enable simultaneous*/
500 if (hwconfig("sdhc"))
502 if (hwconfig("iic2"))
504 if (conflict_flag > 1) {
505 printf("WARNING: pin conflict !\n");
510 if (hwconfig("rgmii"))
516 if (conflict_flag > 1) {
517 printf("WARNING: pin conflict !\n");
522 config_board_mux(MUX_TYPE_CAN);
523 else if (hwconfig("rgmii"))
524 config_board_mux(MUX_TYPE_RGMII);
525 else if (hwconfig("sai"))
526 config_board_mux(MUX_TYPE_SAI);
528 if (hwconfig("iic2"))
529 config_board_mux(MUX_TYPE_IIC2);
530 else if (hwconfig("sdhc"))
531 config_board_mux(MUX_TYPE_SDHC);
533 #ifdef CONFIG_FSL_CAAM
539 struct liodn_id_table sec_liodn_tbl[] = {
540 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
541 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
542 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
543 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
544 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
545 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
546 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
547 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
548 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
549 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
550 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
551 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
552 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
553 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
554 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
555 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
558 struct smmu_stream_id dev_stream_id[] = {
559 { 0x100, 0x01, "ETSEC MAC1" },
560 { 0x104, 0x02, "ETSEC MAC2" },
561 { 0x108, 0x03, "ETSEC MAC3" },
562 { 0x10c, 0x04, "PEX1" },
563 { 0x110, 0x05, "PEX2" },
564 { 0x114, 0x06, "qDMA" },
565 { 0x118, 0x07, "SATA" },
566 { 0x11c, 0x08, "USB3" },
567 { 0x120, 0x09, "QE" },
568 { 0x124, 0x0a, "eSDHC" },
569 { 0x128, 0x0b, "eMA" },
570 { 0x14c, 0x0c, "2D-ACE" },
571 { 0x150, 0x0d, "USB2" },
572 { 0x18c, 0x0e, "DEBUG" },
577 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
580 major = get_soc_major_rev();
581 if (major == SOC_MAJOR_VER_1_0) {
582 /* Set CCI-400 control override register to
583 * enable barrier transaction */
584 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
587 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
589 #ifndef CONFIG_SYS_FSL_NO_SERDES
594 ls1021x_config_caam_stream_id(sec_liodn_tbl,
595 ARRAY_SIZE(sec_liodn_tbl));
596 ls102xa_config_smmu_stream_id(dev_stream_id,
597 ARRAY_SIZE(dev_stream_id));
599 #ifdef CONFIG_LS102XA_NS_ACCESS
600 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
610 #if defined(CONFIG_DEEP_SLEEP)
611 void board_sleep_prepare(void)
613 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
616 major = get_soc_major_rev();
617 if (major == SOC_MAJOR_VER_1_0) {
618 /* Set CCI-400 control override register to
619 * enable barrier transaction */
620 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
624 #ifdef CONFIG_LS102XA_NS_ACCESS
625 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
630 int ft_board_setup(void *blob, bd_t *bd)
632 ft_cpu_setup(blob, bd);
635 ft_pci_setup(blob, bd);
641 u8 flash_read8(void *addr)
643 return __raw_readb(addr + 1);
646 void flash_write16(u16 val, void *addr)
648 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
650 __raw_writew(shftval, addr);
653 u16 flash_read16(void *addr)
655 u16 val = __raw_readw(addr);
657 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);