1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 #include <clock_legacy.h>
9 #include <fdt_support.h>
14 #include <asm/arch/immap_ls102xa.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/ls102xa_soc.h>
18 #include <asm/arch/ls102xa_devdis.h>
25 #include <fsl_devdis.h>
26 #include <fsl_validate.h>
28 #include "../common/i2c_mux.h"
29 #include "../common/sleep.h"
30 #include "../common/qixis.h"
31 #include "ls1021aqds_qixis.h"
36 #define PIN_MUX_SEL_CAN 0x03
37 #define PIN_MUX_SEL_IIC2 0xa0
38 #define PIN_MUX_SEL_RGMII 0x00
39 #define PIN_MUX_SEL_SAI 0x0c
40 #define PIN_MUX_SEL_SDHC 0x00
42 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
43 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
51 MUX_TYPE_SD_PC_SA_SG_SG,
52 MUX_TYPE_SD_PC_SA_PC_SG,
64 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
67 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
71 puts("Board: LS1021AQDS\n");
75 #elif CONFIG_QSPI_BOOT
78 sw = QIXIS_READ(brdcfg[0]);
79 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
82 printf("vBank: %d\n", sw);
90 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
93 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
94 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
95 QIXIS_READ(id), QIXIS_READ(arch));
97 printf("FPGA: v%d (%s), build %d\n",
98 (int)QIXIS_READ(scver), qixis_read_tag(buf),
99 (int)qixis_read_minor());
105 unsigned long get_board_sys_clk(void)
107 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
109 switch (sysclk_conf & 0x0f) {
110 case QIXIS_SYSCLK_64:
112 case QIXIS_SYSCLK_83:
114 case QIXIS_SYSCLK_100:
116 case QIXIS_SYSCLK_125:
118 case QIXIS_SYSCLK_133:
120 case QIXIS_SYSCLK_150:
122 case QIXIS_SYSCLK_160:
124 case QIXIS_SYSCLK_166:
130 #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
131 unsigned long get_board_ddr_clk(void)
133 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
135 switch ((ddrclk_conf & 0x30) >> 4) {
136 case QIXIS_DDRCLK_100:
138 case QIXIS_DDRCLK_125:
140 case QIXIS_DDRCLK_133:
150 * When resuming from deep sleep, the I2C channel may not be
151 * in the default channel. So, switch to the default channel
152 * before accessing DDR SPD.
154 * PCA9547(0x77) mount on I2C1 bus
156 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
157 return fsl_initdram();
160 int board_early_init_f(void)
162 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
164 #ifdef CONFIG_TSEC_ENET
165 /* clear BD & FR bits for BE BD's and frame data */
166 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
169 #ifdef CONFIG_FSL_IFC
170 init_early_memctl_regs();
175 #if defined(CONFIG_DEEP_SLEEP)
177 fsl_dp_disable_console();
183 #ifdef CONFIG_SPL_BUILD
184 void board_init_f(ulong dummy)
186 #ifdef CONFIG_NAND_BOOT
187 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
191 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
192 * NAND boot because IFC signals > IFC_AD7 are not enabled.
193 * This workaround changes RCW source to make all signals enabled.
195 porsr1 = in_be32(&gur->porsr1);
196 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
197 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
198 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
203 memset(__bss_start, 0, __bss_end - __bss_start);
205 #ifdef CONFIG_FSL_IFC
206 init_early_memctl_regs();
211 #if defined(CONFIG_DEEP_SLEEP)
213 fsl_dp_disable_console();
216 preloader_console_init();
218 #ifdef CONFIG_SPL_I2C
225 /* Allow OCRAM access permission as R/W */
226 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
227 enable_layerscape_ns_access();
230 board_init_r(NULL, 0);
234 void config_etseccm_source(int etsec_gtx_125_mux)
236 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
238 switch (etsec_gtx_125_mux) {
240 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
241 debug("etseccm set to GE0_CLK125\n");
245 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
246 debug("etseccm set to GE2_CLK125\n");
250 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
251 debug("etseccm set to GE1_CLK125\n");
255 printf("Error! trying to set etseccm to invalid value\n");
260 int config_board_mux(int ctrl_type)
264 reg12 = QIXIS_READ(brdcfg[12]);
265 reg14 = QIXIS_READ(brdcfg[14]);
269 config_etseccm_source(GE2_CLK125);
270 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
273 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
276 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
279 config_etseccm_source(GE2_CLK125);
280 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
283 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
285 case MUX_TYPE_SD_PCI4:
288 case MUX_TYPE_SD_PC_SA_SG_SG:
291 case MUX_TYPE_SD_PC_SA_PC_SG:
294 case MUX_TYPE_SD_PC_SG_SG:
298 printf("Wrong mux interface type\n");
302 QIXIS_WRITE(brdcfg[12], reg12);
303 QIXIS_WRITE(brdcfg[14], reg14);
308 int config_serdes_mux(void)
310 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
313 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
314 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
318 config_board_mux(MUX_TYPE_SD_PCI4);
321 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
324 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
327 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
330 printf("SRDS1 prtcl:0x%x\n", cfg);
337 #ifdef CONFIG_BOARD_LATE_INIT
338 int board_late_init(void)
340 #ifdef CONFIG_CHAIN_OF_TRUST
341 fsl_setenv_chain_of_trust();
348 int misc_init_r(void)
352 /* some signals can not enable simultaneous*/
354 if (hwconfig("sdhc"))
356 if (hwconfig("iic2"))
358 if (conflict_flag > 1) {
359 printf("WARNING: pin conflict !\n");
364 if (hwconfig("rgmii"))
370 if (conflict_flag > 1) {
371 printf("WARNING: pin conflict !\n");
376 config_board_mux(MUX_TYPE_CAN);
377 else if (hwconfig("rgmii"))
378 config_board_mux(MUX_TYPE_RGMII);
379 else if (hwconfig("sai"))
380 config_board_mux(MUX_TYPE_SAI);
382 if (hwconfig("iic2"))
383 config_board_mux(MUX_TYPE_IIC2);
384 else if (hwconfig("sdhc"))
385 config_board_mux(MUX_TYPE_SDHC);
387 #ifdef CONFIG_FSL_DEVICE_DISABLE
388 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
390 #ifdef CONFIG_FSL_CAAM
398 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
401 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
402 erratum_a009942_check_cpo();
405 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
407 #ifndef CONFIG_SYS_FSL_NO_SERDES
412 ls102xa_smmu_stream_id_init();
421 #if defined(CONFIG_DEEP_SLEEP)
422 void board_sleep_prepare(void)
424 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
425 enable_layerscape_ns_access();
430 int ft_board_setup(void *blob, struct bd_info *bd)
432 ft_cpu_setup(blob, bd);
435 ft_pci_setup(blob, bd);
441 u8 flash_read8(void *addr)
443 return __raw_readb(addr + 1);
446 void flash_write16(u16 val, void *addr)
448 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
450 __raw_writew(shftval, addr);
453 u16 flash_read16(void *addr)
455 u16 val = __raw_readw(addr);
457 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);