2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_stream_id.h>
14 #include <asm/arch/ls102xa_devdis.h>
15 #include <asm/arch/ls102xa_sata.h>
19 #include <fsl_esdhc.h>
23 #include <fsl_devdis.h>
25 #include "../common/sleep.h"
26 #include "../common/qixis.h"
27 #include "ls1021aqds_qixis.h"
29 #include "../../../drivers/qe/qe.h"
32 #define PIN_MUX_SEL_CAN 0x03
33 #define PIN_MUX_SEL_IIC2 0xa0
34 #define PIN_MUX_SEL_RGMII 0x00
35 #define PIN_MUX_SEL_SAI 0x0c
36 #define PIN_MUX_SEL_SDHC 0x00
38 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
39 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
40 DECLARE_GLOBAL_DATA_PTR;
49 MUX_TYPE_SD_PC_SA_SG_SG,
50 MUX_TYPE_SD_PC_SA_PC_SG,
62 #ifndef CONFIG_QSPI_BOOT
65 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
69 puts("Board: LS1021AQDS\n");
73 #elif CONFIG_QSPI_BOOT
76 sw = QIXIS_READ(brdcfg[0]);
77 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
80 printf("vBank: %d\n", sw);
88 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
91 #ifndef CONFIG_QSPI_BOOT
92 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
93 QIXIS_READ(id), QIXIS_READ(arch));
95 printf("FPGA: v%d (%s), build %d\n",
96 (int)QIXIS_READ(scver), qixis_read_tag(buf),
97 (int)qixis_read_minor());
103 unsigned long get_board_sys_clk(void)
105 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
107 switch (sysclk_conf & 0x0f) {
108 case QIXIS_SYSCLK_64:
110 case QIXIS_SYSCLK_83:
112 case QIXIS_SYSCLK_100:
114 case QIXIS_SYSCLK_125:
116 case QIXIS_SYSCLK_133:
118 case QIXIS_SYSCLK_150:
120 case QIXIS_SYSCLK_160:
122 case QIXIS_SYSCLK_166:
128 unsigned long get_board_ddr_clk(void)
130 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
132 switch ((ddrclk_conf & 0x30) >> 4) {
133 case QIXIS_DDRCLK_100:
135 case QIXIS_DDRCLK_125:
137 case QIXIS_DDRCLK_133:
143 unsigned int get_soc_major_rev(void)
145 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
146 unsigned int svr, major;
148 svr = in_be32(&gur->svr);
149 major = SVR_MAJ(svr);
154 int select_i2c_ch_pca9547(u8 ch)
158 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
160 puts("PCA: failed to select proper channel\n");
170 * When resuming from deep sleep, the I2C channel may not be
171 * in the default channel. So, switch to the default channel
172 * before accessing DDR SPD.
174 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
175 gd->ram_size = initdram(0);
180 #ifdef CONFIG_FSL_ESDHC
181 struct fsl_esdhc_cfg esdhc_cfg[1] = {
182 {CONFIG_SYS_FSL_ESDHC_ADDR},
185 int board_mmc_init(bd_t *bis)
187 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
189 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
193 int board_early_init_f(void)
195 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
196 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
199 #ifdef CONFIG_TSEC_ENET
200 /* clear BD & FR bits for BE BD's and frame data */
201 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
204 #ifdef CONFIG_FSL_IFC
205 init_early_memctl_regs();
208 #ifdef CONFIG_FSL_QSPI
209 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
212 #ifdef CONFIG_FSL_DCU_FB
213 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
216 /* Configure Little endian for SAI, ASRC and SPDIF */
217 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
220 * Enable snoop requests and DVM message requests for
221 * Slave insterface S4 (A7 core cluster)
223 out_le32(&cci->slave[4].snoop_ctrl,
224 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
226 major = get_soc_major_rev();
227 if (major == SOC_MAJOR_VER_1_0) {
229 * Set CCI-400 Slave interface S1, S2 Shareable Override
230 * Register All transactions are treated as non-shareable
232 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
233 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
235 /* Workaround for the issue that DDR could not respond to
236 * barrier transaction which is generated by executing DSB/ISB
237 * instruction. Set CCI-400 control override register to
238 * terminate the barrier transaction. After DDR is initialized,
239 * allow barrier transaction to DDR again */
240 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
243 #if defined(CONFIG_DEEP_SLEEP)
245 fsl_dp_disable_console();
251 #ifdef CONFIG_SPL_BUILD
252 void board_init_f(ulong dummy)
254 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
257 #ifdef CONFIG_NAND_BOOT
258 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
262 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
263 * NAND boot because IFC signals > IFC_AD7 are not enabled.
264 * This workaround changes RCW source to make all signals enabled.
266 porsr1 = in_be32(&gur->porsr1);
267 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
268 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
269 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
274 memset(__bss_start, 0, __bss_end - __bss_start);
276 #ifdef CONFIG_FSL_IFC
277 init_early_memctl_regs();
282 #if defined(CONFIG_DEEP_SLEEP)
284 fsl_dp_disable_console();
287 preloader_console_init();
289 #ifdef CONFIG_SPL_I2C_SUPPORT
293 major = get_soc_major_rev();
294 if (major == SOC_MAJOR_VER_1_0)
295 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
299 /* Allow OCRAM access permission as R/W */
300 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
301 enable_layerscape_ns_access();
304 board_init_r(NULL, 0);
308 void config_etseccm_source(int etsec_gtx_125_mux)
310 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
312 switch (etsec_gtx_125_mux) {
314 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
315 debug("etseccm set to GE0_CLK125\n");
319 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
320 debug("etseccm set to GE2_CLK125\n");
324 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
325 debug("etseccm set to GE1_CLK125\n");
329 printf("Error! trying to set etseccm to invalid value\n");
334 int config_board_mux(int ctrl_type)
338 reg12 = QIXIS_READ(brdcfg[12]);
339 reg14 = QIXIS_READ(brdcfg[14]);
343 config_etseccm_source(GE2_CLK125);
344 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
347 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
350 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
353 config_etseccm_source(GE2_CLK125);
354 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
357 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
359 case MUX_TYPE_SD_PCI4:
362 case MUX_TYPE_SD_PC_SA_SG_SG:
365 case MUX_TYPE_SD_PC_SA_PC_SG:
368 case MUX_TYPE_SD_PC_SG_SG:
372 printf("Wrong mux interface type\n");
376 QIXIS_WRITE(brdcfg[12], reg12);
377 QIXIS_WRITE(brdcfg[14], reg14);
382 int config_serdes_mux(void)
384 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
387 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
388 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
392 config_board_mux(MUX_TYPE_SD_PCI4);
395 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
398 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
401 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
404 printf("SRDS1 prtcl:0x%x\n", cfg);
411 #ifdef CONFIG_BOARD_LATE_INIT
412 int board_late_init(void)
414 #ifdef CONFIG_SCSI_AHCI_PLAT
422 int misc_init_r(void)
426 /* some signals can not enable simultaneous*/
428 if (hwconfig("sdhc"))
430 if (hwconfig("iic2"))
432 if (conflict_flag > 1) {
433 printf("WARNING: pin conflict !\n");
438 if (hwconfig("rgmii"))
444 if (conflict_flag > 1) {
445 printf("WARNING: pin conflict !\n");
450 config_board_mux(MUX_TYPE_CAN);
451 else if (hwconfig("rgmii"))
452 config_board_mux(MUX_TYPE_RGMII);
453 else if (hwconfig("sai"))
454 config_board_mux(MUX_TYPE_SAI);
456 if (hwconfig("iic2"))
457 config_board_mux(MUX_TYPE_IIC2);
458 else if (hwconfig("sdhc"))
459 config_board_mux(MUX_TYPE_SDHC);
461 #ifdef CONFIG_FSL_DEVICE_DISABLE
462 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
464 #ifdef CONFIG_FSL_CAAM
470 struct liodn_id_table sec_liodn_tbl[] = {
471 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
472 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
473 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
474 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
475 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
476 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
477 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
478 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
479 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
480 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
481 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
482 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
483 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
484 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
485 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
486 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
489 struct smmu_stream_id dev_stream_id[] = {
490 { 0x100, 0x01, "ETSEC MAC1" },
491 { 0x104, 0x02, "ETSEC MAC2" },
492 { 0x108, 0x03, "ETSEC MAC3" },
493 { 0x10c, 0x04, "PEX1" },
494 { 0x110, 0x05, "PEX2" },
495 { 0x114, 0x06, "qDMA" },
496 { 0x118, 0x07, "SATA" },
497 { 0x11c, 0x08, "USB3" },
498 { 0x120, 0x09, "QE" },
499 { 0x124, 0x0a, "eSDHC" },
500 { 0x128, 0x0b, "eMA" },
501 { 0x14c, 0x0c, "2D-ACE" },
502 { 0x150, 0x0d, "USB2" },
503 { 0x18c, 0x0e, "DEBUG" },
508 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
511 major = get_soc_major_rev();
512 if (major == SOC_MAJOR_VER_1_0) {
513 /* Set CCI-400 control override register to
514 * enable barrier transaction */
515 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
518 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
520 #ifndef CONFIG_SYS_FSL_NO_SERDES
525 ls1021x_config_caam_stream_id(sec_liodn_tbl,
526 ARRAY_SIZE(sec_liodn_tbl));
527 ls102xa_config_smmu_stream_id(dev_stream_id,
528 ARRAY_SIZE(dev_stream_id));
530 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
531 enable_layerscape_ns_access();
541 #if defined(CONFIG_DEEP_SLEEP)
542 void board_sleep_prepare(void)
544 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
547 major = get_soc_major_rev();
548 if (major == SOC_MAJOR_VER_1_0) {
549 /* Set CCI-400 control override register to
550 * enable barrier transaction */
551 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
555 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
556 enable_layerscape_ns_access();
561 int ft_board_setup(void *blob, bd_t *bd)
563 ft_cpu_setup(blob, bd);
566 ft_pci_setup(blob, bd);
572 u8 flash_read8(void *addr)
574 return __raw_readb(addr + 1);
577 void flash_write16(u16 val, void *addr)
579 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
581 __raw_writew(shftval, addr);
584 u16 flash_read16(void *addr)
586 u16 val = __raw_readw(addr);
588 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);