2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
14 #include <fsl_esdhc.h>
18 #include "../common/qixis.h"
19 #include "ls1021aqds_qixis.h"
21 DECLARE_GLOBAL_DATA_PTR;
25 MUX_TYPE_SD_PC_SA_SG_SG,
26 MUX_TYPE_SD_PC_SA_PC_SG,
35 puts("Board: LS1021AQDS\n");
37 sw = QIXIS_READ(brdcfg[0]);
38 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
41 printf("vBank: %d\n", sw);
49 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
51 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
52 QIXIS_READ(id), QIXIS_READ(arch));
54 printf("FPGA: v%d (%s), build %d\n",
55 (int)QIXIS_READ(scver), qixis_read_tag(buf),
56 (int)qixis_read_minor());
61 unsigned long get_board_sys_clk(void)
63 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
65 switch (sysclk_conf & 0x0f) {
70 case QIXIS_SYSCLK_100:
72 case QIXIS_SYSCLK_125:
74 case QIXIS_SYSCLK_133:
76 case QIXIS_SYSCLK_150:
78 case QIXIS_SYSCLK_160:
80 case QIXIS_SYSCLK_166:
86 unsigned long get_board_ddr_clk(void)
88 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
90 switch ((ddrclk_conf & 0x30) >> 4) {
91 case QIXIS_DDRCLK_100:
93 case QIXIS_DDRCLK_125:
95 case QIXIS_DDRCLK_133:
103 gd->ram_size = initdram(0);
108 #ifdef CONFIG_FSL_ESDHC
109 struct fsl_esdhc_cfg esdhc_cfg[1] = {
110 {CONFIG_SYS_FSL_ESDHC_ADDR},
113 int board_mmc_init(bd_t *bis)
115 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
117 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
121 int select_i2c_ch_pca9547(u8 ch)
125 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
127 puts("PCA: failed to select proper channel\n");
134 int board_early_init_f(void)
136 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
137 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
139 #ifdef CONFIG_TSEC_ENET
140 out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
141 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
142 out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
145 #ifdef CONFIG_FSL_IFC
146 init_early_memctl_regs();
149 /* Workaround for the issue that DDR could not respond to
150 * barrier transaction which is generated by executing DSB/ISB
151 * instruction. Set CCI-400 control override register to
152 * terminate the barrier transaction. After DDR is initialized,
153 * allow barrier transaction to DDR again */
154 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
159 int config_board_mux(int ctrl_type)
163 reg12 = QIXIS_READ(brdcfg[12]);
166 case MUX_TYPE_SD_PCI4:
169 case MUX_TYPE_SD_PC_SA_SG_SG:
172 case MUX_TYPE_SD_PC_SA_PC_SG:
175 case MUX_TYPE_SD_PC_SG_SG:
179 printf("Wrong mux interface type\n");
183 QIXIS_WRITE(brdcfg[12], reg12);
188 int config_serdes_mux(void)
190 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
193 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
194 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
198 config_board_mux(MUX_TYPE_SD_PCI4);
201 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
204 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
207 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
210 printf("SRDS1 prtcl:0x%x\n", cfg);
217 #if defined(CONFIG_MISC_INIT_R)
218 int misc_init_r(void)
220 #ifdef CONFIG_FSL_CAAM
228 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
230 /* Set CCI-400 control override register to
231 * enable barrier transaction */
232 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
234 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
236 #ifndef CONFIG_SYS_FSL_NO_SERDES
243 void ft_board_setup(void *blob, bd_t *bd)
245 ft_cpu_setup(blob, bd);
248 u8 flash_read8(void *addr)
250 return __raw_readb(addr + 1);
253 void flash_write16(u16 val, void *addr)
255 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
257 __raw_writew(shftval, addr);
260 u16 flash_read16(void *addr)
262 u16 val = __raw_readw(addr);
264 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);