board/freescale/ls1021aqds/ls1021aqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <asm/pcie_layerscape.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <fsl_ifc.h>
  20 #include <fsl_sec.h>
  21 #include <spl.h>
  22
  23 #include "../common/sleep.h"
  24 #include "../common/qixis.h"
  25 #include "ls1021aqds_qixis.h"
  26 #ifdef CONFIG_U_QE
  27 #include "../../../drivers/qe/qe.h"
  28 #endif
  29
  30 #define PIN_MUX_SEL_CAN         0x03
  31 #define PIN_MUX_SEL_IIC2        0xa0
  32 #define PIN_MUX_SEL_RGMII       0x00
  33 #define PIN_MUX_SEL_SAI         0x0c
  34 #define PIN_MUX_SEL_SDHC        0x00
  35
  36 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0x0f) | value)
  37 #define SET_EC_MUX_SEL(reg, value)      ((reg & 0xf0) | value)
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 enum {
  41         MUX_TYPE_CAN,
  42         MUX_TYPE_IIC2,
  43         MUX_TYPE_RGMII,
  44         MUX_TYPE_SAI,
  45         MUX_TYPE_SDHC,
  46         MUX_TYPE_SD_PCI4,
  47         MUX_TYPE_SD_PC_SA_SG_SG,
  48         MUX_TYPE_SD_PC_SA_PC_SG,
  49         MUX_TYPE_SD_PC_SG_SG,
  50 };
  51
  52 enum {
  53         GE0_CLK125,
  54         GE2_CLK125,
  55         GE1_CLK125,
  56 };
  57
  58 int checkboard(void)
  59 {
  60 #ifndef CONFIG_QSPI_BOOT
  61         char buf[64];
  62 #endif
  63 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  64         u8 sw;
  65 #endif
  66
  67         puts("Board: LS1021AQDS\n");
  68
  69 #ifdef CONFIG_SD_BOOT
  70         puts("SD\n");
  71 #elif CONFIG_QSPI_BOOT
  72         puts("QSPI\n");
  73 #else
  74         sw = QIXIS_READ(brdcfg[0]);
  75         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  76
  77         if (sw < 0x8)
  78                 printf("vBank: %d\n", sw);
  79         else if (sw == 0x8)
  80                 puts("PromJet\n");
  81         else if (sw == 0x9)
  82                 puts("NAND\n");
  83         else if (sw == 0x15)
  84                 printf("IFCCard\n");
  85         else
  86                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  87 #endif
  88
  89 #ifndef CONFIG_QSPI_BOOT
  90         printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  91                QIXIS_READ(id), QIXIS_READ(arch));
  92
  93         printf("FPGA:  v%d (%s), build %d\n",
  94                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  95                (int)qixis_read_minor());
  96 #endif
  97
  98         return 0;
  99 }
 100
 101 unsigned long get_board_sys_clk(void)
 102 {
 103         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 104
 105         switch (sysclk_conf & 0x0f) {
 106         case QIXIS_SYSCLK_64:
 107                 return 64000000;
 108         case QIXIS_SYSCLK_83:
 109                 return 83333333;
 110         case QIXIS_SYSCLK_100:
 111                 return 100000000;
 112         case QIXIS_SYSCLK_125:
 113                 return 125000000;
 114         case QIXIS_SYSCLK_133:
 115                 return 133333333;
 116         case QIXIS_SYSCLK_150:
 117                 return 150000000;
 118         case QIXIS_SYSCLK_160:
 119                 return 160000000;
 120         case QIXIS_SYSCLK_166:
 121                 return 166666666;
 122         }
 123         return 66666666;
 124 }
 125
 126 unsigned long get_board_ddr_clk(void)
 127 {
 128         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 129
 130         switch ((ddrclk_conf & 0x30) >> 4) {
 131         case QIXIS_DDRCLK_100:
 132                 return 100000000;
 133         case QIXIS_DDRCLK_125:
 134                 return 125000000;
 135         case QIXIS_DDRCLK_133:
 136                 return 133333333;
 137         }
 138         return 66666666;
 139 }
 140
 141 unsigned int get_soc_major_rev(void)
 142 {
 143         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 144         unsigned int svr, major;
 145
 146         svr = in_be32(&gur->svr);
 147         major = SVR_MAJ(svr);
 148
 149         return major;
 150 }
 151
 152 int select_i2c_ch_pca9547(u8 ch)
 153 {
 154         int ret;
 155
 156         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 157         if (ret) {
 158                 puts("PCA: failed to select proper channel\n");
 159                 return ret;
 160         }
 161
 162         return 0;
 163 }
 164
 165 int dram_init(void)
 166 {
 167         /*
 168          * When resuming from deep sleep, the I2C channel may not be
 169          * in the default channel. So, switch to the default channel
 170          * before accessing DDR SPD.
 171          */
 172         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 173         gd->ram_size = initdram(0);
 174
 175         return 0;
 176 }
 177
 178 #ifdef CONFIG_FSL_ESDHC
 179 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 180         {CONFIG_SYS_FSL_ESDHC_ADDR},
 181 };
 182
 183 int board_mmc_init(bd_t *bis)
 184 {
 185         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 186
 187         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 188 }
 189 #endif
 190
 191 int board_early_init_f(void)
 192 {
 193         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 194         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 195         unsigned int major;
 196
 197 #ifdef CONFIG_TSEC_ENET
 198         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 199 #endif
 200
 201 #ifdef CONFIG_FSL_IFC
 202         init_early_memctl_regs();
 203 #endif
 204
 205 #ifdef CONFIG_FSL_QSPI
 206         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 207 #endif
 208
 209 #ifdef CONFIG_FSL_DCU_FB
 210         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 211 #endif
 212
 213         /*
 214          * Enable snoop requests and DVM message requests for
 215          * Slave insterface S4 (A7 core cluster)
 216          */
 217         out_le32(&cci->slave[4].snoop_ctrl,
 218                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 219
 220         major = get_soc_major_rev();
 221         if (major == SOC_MAJOR_VER_1_0) {
 222                 /*
 223                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 224                  * Register All transactions are treated as non-shareable
 225                  */
 226                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 227                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 228
 229                 /* Workaround for the issue that DDR could not respond to
 230                  * barrier transaction which is generated by executing DSB/ISB
 231                  * instruction. Set CCI-400 control override register to
 232                  * terminate the barrier transaction. After DDR is initialized,
 233                  * allow barrier transaction to DDR again */
 234                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 235         }
 236
 237 #if defined(CONFIG_DEEP_SLEEP)
 238         if (is_warm_boot())
 239                 fsl_dp_disable_console();
 240 #endif
 241
 242         return 0;
 243 }
 244
 245 #ifdef CONFIG_SPL_BUILD
 246 void board_init_f(ulong dummy)
 247 {
 248         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 249         unsigned int major;
 250
 251 #ifdef CONFIG_NAND_BOOT
 252         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 253         u32 porsr1, pinctl;
 254
 255         /*
 256          * There is LS1 SoC issue where NOR, FPGA are inaccessible during
 257          * NAND boot because IFC signals > IFC_AD7 are not enabled.
 258          * This workaround changes RCW source to make all signals enabled.
 259          */
 260         porsr1 = in_be32(&gur->porsr1);
 261         pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
 262                  DCFG_CCSR_PORSR1_RCW_SRC_I2C);
 263         out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 264                  pinctl);
 265 #endif
 266
 267         /* Clear the BSS */
 268         memset(__bss_start, 0, __bss_end - __bss_start);
 269
 270 #ifdef CONFIG_FSL_IFC
 271         init_early_memctl_regs();
 272 #endif
 273
 274         get_clocks();
 275
 276 #if defined(CONFIG_DEEP_SLEEP)
 277         if (is_warm_boot())
 278                 fsl_dp_disable_console();
 279 #endif
 280
 281         preloader_console_init();
 282
 283 #ifdef CONFIG_SPL_I2C_SUPPORT
 284         i2c_init_all();
 285 #endif
 286
 287         major = get_soc_major_rev();
 288         if (major == SOC_MAJOR_VER_1_0)
 289                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 290
 291         dram_init();
 292
 293         board_init_r(NULL, 0);
 294 }
 295 #endif
 296
 297 void config_etseccm_source(int etsec_gtx_125_mux)
 298 {
 299         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 300
 301         switch (etsec_gtx_125_mux) {
 302         case GE0_CLK125:
 303                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
 304                 debug("etseccm set to GE0_CLK125\n");
 305                 break;
 306
 307         case GE2_CLK125:
 308                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 309                 debug("etseccm set to GE2_CLK125\n");
 310                 break;
 311
 312         case GE1_CLK125:
 313                 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
 314                 debug("etseccm set to GE1_CLK125\n");
 315                 break;
 316
 317         default:
 318                 printf("Error! trying to set etseccm to invalid value\n");
 319                 break;
 320         }
 321 }
 322
 323 int config_board_mux(int ctrl_type)
 324 {
 325         u8 reg12, reg14;
 326
 327         reg12 = QIXIS_READ(brdcfg[12]);
 328         reg14 = QIXIS_READ(brdcfg[14]);
 329
 330         switch (ctrl_type) {
 331         case MUX_TYPE_CAN:
 332                 config_etseccm_source(GE2_CLK125);
 333                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
 334                 break;
 335         case MUX_TYPE_IIC2:
 336                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
 337                 break;
 338         case MUX_TYPE_RGMII:
 339                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
 340                 break;
 341         case MUX_TYPE_SAI:
 342                 config_etseccm_source(GE2_CLK125);
 343                 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
 344                 break;
 345         case MUX_TYPE_SDHC:
 346                 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
 347                 break;
 348         case MUX_TYPE_SD_PCI4:
 349                 reg12 = 0x38;
 350                 break;
 351         case MUX_TYPE_SD_PC_SA_SG_SG:
 352                 reg12 = 0x01;
 353                 break;
 354         case MUX_TYPE_SD_PC_SA_PC_SG:
 355                 reg12 = 0x01;
 356                 break;
 357         case MUX_TYPE_SD_PC_SG_SG:
 358                 reg12 = 0x21;
 359                 break;
 360         default:
 361                 printf("Wrong mux interface type\n");
 362                 return -1;
 363         }
 364
 365         QIXIS_WRITE(brdcfg[12], reg12);
 366         QIXIS_WRITE(brdcfg[14], reg14);
 367
 368         return 0;
 369 }
 370
 371 int config_serdes_mux(void)
 372 {
 373         struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
 374         u32 cfg;
 375
 376         cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 377         cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 378
 379         switch (cfg) {
 380         case 0x0:
 381                 config_board_mux(MUX_TYPE_SD_PCI4);
 382                 break;
 383         case 0x30:
 384                 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
 385                 break;
 386         case 0x60:
 387                 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
 388                 break;
 389         case 0x70:
 390                 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
 391                 break;
 392         default:
 393                 printf("SRDS1 prtcl:0x%x\n", cfg);
 394                 break;
 395         }
 396
 397         return 0;
 398 }
 399
 400 int misc_init_r(void)
 401 {
 402         int conflict_flag;
 403
 404         /* some signals can not enable simultaneous*/
 405         conflict_flag = 0;
 406         if (hwconfig("sdhc"))
 407                 conflict_flag++;
 408         if (hwconfig("iic2"))
 409                 conflict_flag++;
 410         if (conflict_flag > 1) {
 411                 printf("WARNING: pin conflict !\n");
 412                 return 0;
 413         }
 414
 415         conflict_flag = 0;
 416         if (hwconfig("rgmii"))
 417                 conflict_flag++;
 418         if (hwconfig("can"))
 419                 conflict_flag++;
 420         if (hwconfig("sai"))
 421                 conflict_flag++;
 422         if (conflict_flag > 1) {
 423                 printf("WARNING: pin conflict !\n");
 424                 return 0;
 425         }
 426
 427         if (hwconfig("can"))
 428                 config_board_mux(MUX_TYPE_CAN);
 429         else if (hwconfig("rgmii"))
 430                 config_board_mux(MUX_TYPE_RGMII);
 431         else if (hwconfig("sai"))
 432                 config_board_mux(MUX_TYPE_SAI);
 433
 434         if (hwconfig("iic2"))
 435                 config_board_mux(MUX_TYPE_IIC2);
 436         else if (hwconfig("sdhc"))
 437                 config_board_mux(MUX_TYPE_SDHC);
 438
 439 #ifdef CONFIG_FSL_CAAM
 440         return sec_init();
 441 #endif
 442         return 0;
 443 }
 444
 445 #ifdef CONFIG_LS102XA_NS_ACCESS
 446 static struct csu_ns_dev ns_dev[] = {
 447         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 448         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 449         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 450         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 451         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 452         { CSU_CSLX_GIC, CSU_ALL_RW },
 453         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 454         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 455         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 456         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 457         { CSU_CSLX_SATA, CSU_ALL_RW },
 458         { CSU_CSLX_USB3, CSU_ALL_RW },
 459         { CSU_CSLX_SERDES, CSU_ALL_RW },
 460         { CSU_CSLX_QDMA, CSU_ALL_RW },
 461         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 462         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 463         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 464         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 465         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 466         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 467         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 468         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 469         { CSU_CSLX_QSPI, CSU_ALL_RW },
 470         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 471         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 472         { CSU_CSLX_IFC, CSU_ALL_RW },
 473         { CSU_CSLX_I2C1, CSU_ALL_RW },
 474         { CSU_CSLX_USB2, CSU_ALL_RW },
 475         { CSU_CSLX_I2C3, CSU_ALL_RW },
 476         { CSU_CSLX_I2C2, CSU_ALL_RW },
 477         { CSU_CSLX_DUART2, CSU_ALL_RW },
 478         { CSU_CSLX_DUART1, CSU_ALL_RW },
 479         { CSU_CSLX_WDT2, CSU_ALL_RW },
 480         { CSU_CSLX_WDT1, CSU_ALL_RW },
 481         { CSU_CSLX_EDMA, CSU_ALL_RW },
 482         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 483         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 484         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 485         { CSU_CSLX_DDR, CSU_ALL_RW },
 486         { CSU_CSLX_QUICC, CSU_ALL_RW },
 487         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 488         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 489         { CSU_CSLX_SFP, CSU_ALL_RW },
 490         { CSU_CSLX_TMU, CSU_ALL_RW },
 491         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 492         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 493         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 494         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 495         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 496         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 497         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 498         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 499         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 500         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 501         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 502         { CSU_CSLX_CSU, CSU_ALL_RW },
 503         { CSU_CSLX_ASRC, CSU_ALL_RW },
 504         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 505         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 506         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 507         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 508         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 509         { CSU_CSLX_SAI2, CSU_ALL_RW },
 510         { CSU_CSLX_SAI1, CSU_ALL_RW },
 511         { CSU_CSLX_SAI4, CSU_ALL_RW },
 512         { CSU_CSLX_SAI3, CSU_ALL_RW },
 513         { CSU_CSLX_FTM2, CSU_ALL_RW },
 514         { CSU_CSLX_FTM1, CSU_ALL_RW },
 515         { CSU_CSLX_FTM4, CSU_ALL_RW },
 516         { CSU_CSLX_FTM3, CSU_ALL_RW },
 517         { CSU_CSLX_FTM6, CSU_ALL_RW },
 518         { CSU_CSLX_FTM5, CSU_ALL_RW },
 519         { CSU_CSLX_FTM8, CSU_ALL_RW },
 520         { CSU_CSLX_FTM7, CSU_ALL_RW },
 521         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 522         { CSU_CSLX_EPU, CSU_ALL_RW },
 523         { CSU_CSLX_GDI, CSU_ALL_RW },
 524         { CSU_CSLX_DDI, CSU_ALL_RW },
 525         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 526         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 527         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 528 };
 529 #endif
 530
 531 struct liodn_id_table sec_liodn_tbl[] = {
 532         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 533         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 534         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 535         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 536         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 537         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 538         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 539         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 540         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 541         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 542         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 543         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 544         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 545         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 546         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 547         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 548 };
 549
 550 struct smmu_stream_id dev_stream_id[] = {
 551         { 0x100, 0x01, "ETSEC MAC1" },
 552         { 0x104, 0x02, "ETSEC MAC2" },
 553         { 0x108, 0x03, "ETSEC MAC3" },
 554         { 0x10c, 0x04, "PEX1" },
 555         { 0x110, 0x05, "PEX2" },
 556         { 0x114, 0x06, "qDMA" },
 557         { 0x118, 0x07, "SATA" },
 558         { 0x11c, 0x08, "USB3" },
 559         { 0x120, 0x09, "QE" },
 560         { 0x124, 0x0a, "eSDHC" },
 561         { 0x128, 0x0b, "eMA" },
 562         { 0x14c, 0x0c, "2D-ACE" },
 563         { 0x150, 0x0d, "USB2" },
 564         { 0x18c, 0x0e, "DEBUG" },
 565 };
 566
 567 int board_init(void)
 568 {
 569         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 570         unsigned int major;
 571
 572         major = get_soc_major_rev();
 573         if (major == SOC_MAJOR_VER_1_0) {
 574                 /* Set CCI-400 control override register to
 575                  * enable barrier transaction */
 576                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 577         }
 578
 579         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 580
 581 #ifndef CONFIG_SYS_FSL_NO_SERDES
 582         fsl_serdes_init();
 583         config_serdes_mux();
 584 #endif
 585
 586         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 587                                       ARRAY_SIZE(sec_liodn_tbl));
 588         ls102xa_config_smmu_stream_id(dev_stream_id,
 589                                       ARRAY_SIZE(dev_stream_id));
 590
 591 #ifdef CONFIG_LS102XA_NS_ACCESS
 592         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 593 #endif
 594
 595 #ifdef CONFIG_U_QE
 596         u_qe_init();
 597 #endif
 598
 599         return 0;
 600 }
 601
 602 #if defined(CONFIG_DEEP_SLEEP)
 603 void board_sleep_prepare(void)
 604 {
 605         struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
 606         unsigned int major;
 607
 608         major = get_soc_major_rev();
 609         if (major == SOC_MAJOR_VER_1_0) {
 610                 /* Set CCI-400 control override register to
 611                  * enable barrier transaction */
 612                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 613         }
 614
 615
 616 #ifdef CONFIG_LS102XA_NS_ACCESS
 617         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 618 #endif
 619 }
 620 #endif
 621
 622 int ft_board_setup(void *blob, bd_t *bd)
 623 {
 624         ft_cpu_setup(blob, bd);
 625
 626 #ifdef CONFIG_PCIE_LAYERSCAPE
 627         ft_pcie_setup(blob, bd);
 628 #endif
 629
 630         return 0;
 631 }
 632
 633 u8 flash_read8(void *addr)
 634 {
 635         return __raw_readb(addr + 1);
 636 }
 637
 638 void flash_write16(u16 val, void *addr)
 639 {
 640         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 641
 642         __raw_writew(shftval, addr);
 643 }
 644
 645 u16 flash_read16(void *addr)
 646 {
 647         u16 val = __raw_readw(addr);
 648
 649         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 650 }